Publications by Paolo Ienne | EPFL Graph Search

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Making Wide-Issue VLIW Processors Viable on FPGAs

Software Controlled Cell Bit-Density to Improve NAND Flash Lifetime

Compressor Tree Synthesis on Commercial High-Performance FPGAs

A First Step Towards Automatic Application of Power Analysis Countermeasures

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

Improving FPGA Performance for Carry-Save Arithmetic

A 5.35 mm2 10GBASE-T Ethernet LDPC Decoder Chip in 90 nm CMOS

An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form

Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions