Yusuf Leblebici

Effect of Native Oxide on Stress in Silicon Nanowires: Implications for Nanoelectromechanical Systems

Yusuf Leblebici, Mohammad Nasr Esfahani, Zuhal Tasdemir

Understanding the origins of intrinsic stress in Si nanowires (NWs) is crucial for their successful utilization as transducer building blocks in next-generation, miniaturized sensors based on nanoelectromechanical systems (NEMS). With their small size leading to ultrahigh-resonance frequencies and extreme surface-to-volume ratios, silicon NWs raise new opportunities regarding sensitivity, precision, and speed in both physical and biochemical sensing. With silicon optoelectromechanical properties strongly dependent on the level of NW intrinsic stress, various studies have been devoted to the measurement of such stresses generated, for example, as a result of harsh fabrication processes. However, due to enormous NW surface area, even the native oxide that is conventionally considered as a benign surface condition can cause significant stresses. To address this issue, a combination of nanomechanical characterization and atomistic simulation approaches is developed. Relying only on low-temperature processes, the fabrication approach yields monolithic NWs with optimum boundary conditions, where NWs and support architecture are etched within the same silicon crystal. Resulting NWs are characterized by transmission electron microscopy and micro-Raman spectroscopy. The interpretation of results is carried out through molecular dynamics simulations with ReaxFF potential facilitating the incorporation of humidity and temperature, thereby providing a close replica of the actual oxidation environment-in contrast to previous dry oxidation or self-limiting thermal oxidation studies. As a result, consensus on significant intrinsic tensile stresses on the order of 100 MPa to 1 GPa was achieved as a function of NW critical dimension and aspect ratio. The understanding developed herein regarding the role of native oxide played in the generation of NW intrinsic stresses is important for the design and development of silicon-based NEMS.

AMER CHEMICAL SOC2022

A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS

Cosimo Aprile, Volkan Cevher, Catherine Dehollain, Florian Dylan Fallegger, Stéphanie Lacour, Yusuf Leblebici, Alix Esther Anne Trouillet, Kerim Türe, Arda Uran

Wireless implantable neural recording chips enable multichannel data acquisition with high spatiotemporal resolution in situ. Recently, the use of machine learning approaches on neural data for diagnosis and prosthesis control have renewed the interest in this field, and increased even more the demand for multichannel data. However, simultaneous data acquisition from many channels is a grand challenge due to data rate and power limitations on wireless transmission for implants. As a result, recent studies have focused on on-chip classifiers (Fig. 1 top), despite the fact that only primitive classifiers can be placed on resource-constrained chips. Moreover, robustness of the chosen algorithm cannot be guaranteed pre-implantation due to the scarcity of patient-specific data; waveforms can change over time due to electrode micro migration or tissue reaction, highlighting the need for robust adaptive features.

2021

A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI

Ayça Akkaya, Firat Çelik, Yusuf Leblebici

This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-digital-converter (ADC) in the RX AFE has an embedded 2-tap analog feed-forward equalizer. The design objective is to optimize the energy efficiency for the target data rate and the moderate-loss channel. For this purpose, the optimum modulation order that has the least ISI sensitivity for the given equalization capability is decided with a modeling study. All the equalization is performed in the analog domain to avoid the circuit complexity and power consumption disadvantages of the digital equalization in the selected high-order modulation. Thanks to the spectral efficiency of PAM-16 and the analog-only equalization, the figure-of-merit is improved significantly. Post-layout simulations show that the TX consumes 26.85 mW while the RX AFE consumes 49.36 mW at 32 Gb/s with PAM-16, which corresponds to 2.38 pJ/bit for the whole system.

2021

A new characterization approach to study the mechanical behavior of silicon nanowires

Yusuf Leblebici, Mohammad Nasr Esfahani, Zuhal Tasdemir, Mustafa Yilmaz

This work proposes a new approach to characterize the mechanical properties of nanowires based on a combination of nanomechanical measurements and models. Silicon nanowires with a critical dimension of 90 nm and a length of 8 mu m obtained through a monolithic process are characterized through in-situ three-point bending tests. A nonlinear nanomechanical model is developed to evaluate the mechanical behavior of nanowires. In this model, the intrinsic stress and surface parameters are examined based on Raman spectroscopy measurements and molecular dynamics simulations, respectively. This work demonstrates a new approach to measure the mechanical properties of Si nanowires by considering the surface effect and intrinsic stresses. The presented technique can be used to address the existing discrepancies between numerical estimations and experimental measurements on the modulus of elasticity of silicon nanowires.

SPRINGER HEIDELBERG2021

An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI

Ayça Akkaya, Firat Çelik, Yusuf Leblebici

This paper presents a low-power single-channel 8-bit loop-unrolled (LU) successive approximation register (SAR) analog-to-digital-converter (ADC) with a novel common-mode adaptive background comparator offset calibration scheme. LU-SAR ADCs use multiple comparators to reduce the SAR loop delay. Offset mismatch between the comparators severely degrades the effective resolution. This paper addresses the common-mode voltage variation in the LU-SAR architecture due to comparator kickback and the problems related to the common-mode dependency of the comparator offset. The proposed offset calibration scheme ensures that the comparators are calibrated at the same input common-mode voltage at which they each operate during the SAR conversion to prevent the common-mode dependent offset mismatch between them. Moreover, the proposed ADC design exploits the common-mode variation immunity of the proposed calibration scheme to optimize the figure-of-merit (FoM). The prototype ADC manufactured in 28nm FDSOI CMOS achieves 42.57dB signal-to-noise-and-distortion ratio and 22.8fJ/conv.-step FoM at 800MS/s with near Nyquist frequency input, and occupies an area of 0.0037mm(2).

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Cosimo Aprile, Andreas Peter Burg, Alessandro Cevrero, Gain Kim, Lukas Kull, Yusuf Leblebici, Ilter Ozkaya, Thomas Toifl

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed and routed digital signal processor (DSP) following a 10-bit time-interleaved pipelined successive-approximation register analog-to-digital converter (TI-PISAR ADC). The prototype RX chip implemented in a 14-nm FinFET process demonstrates a lane data rate of 56 Gb/s dissipating 161 mW including the ADC and the DSP power. The energy efficiency of 1.2 pJ/b for the DSP and 2.9 pJ/b for the entire RX was achieved with the data-rate of 56 Gb/s for communicating over channels exhibiting up to 28-dB loss at 14 GHz with a bit-error-rate (BER) better than 2e-4.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Ayça Akkaya, Firat Çelik, Yusuf Leblebici

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacitors, splitting monotonic capacitor switching, and dynamic SAR memory to optimize both power consumption and SAR loop delay using a single comparator. Measurement results show that the 9-bit SAR ADC achieves 47.6 dB SNDR and 29.6 fJ/conversion-step figure-of-merit (FoM) near Nyquist frequency at 222 MS/s, consuming 1.07 mA from a 1.2 V supply. The ADC does not consume static power and the current consumption scales down linearly with the sampling rate, keeping the low FoM value constant over a very wide sampling frequency range. The design occupies an active area of 92 μm × 180 μm (0.017 mm 2 ) in 65 nm CMOS.

IEEE2020

An AC-Coupled Wideband Neural Recording Front-End With Sub-1 mm2×fJ/conv-step Efficiency and 0.97 NEF

Volkan Cevher, Yusuf Leblebici, Arda Uran

This letter presents an energy-and-area-efficient ac-coupled front-end for the multichannel recording of wideband neural signals. The proposed unit conditions local held and action potentials using an inverter-based capacitively coupled low-noise amplifier, followed by a per-channel 10-b asynchronous SAR ADC. The adaptation of unit-length capacitors minimizes the ADC area and relaxes the amplifier gain so that small coupling capacitors can be integrated. The prototype in 65-nm CMOS achieves 4× smaller area and 3× higher energy-area efficiency compared to the state of the art with 164 μm×40 μm footprint and 0.78 mm 2 ×fJ/conv-step energy-area figure of merit. The measured 0.65-μW power consumption and 3.1-μVrms input-referred noise within 1 Hz-10 kHz bandwidth correspond to a noise efficiency factor of 0.97.

2020

Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL

Duygu Kostak, Yusuf Leblebici

The discrete time analysis of the phase detector linear range extension in the first and the second order sub sampling phase-locked loop (SSPLL) is presented. The aim is to understand how much the stability and the pull-in range are affected by the linear range of the sub -sampled phase detector. To change the linear range, sinusoidal, triangular and sawtooth signals are used as the voltage-controlled oscillator (VCO) output signals. The discrete time domain equations of the first and the second order loops are built and solved to determine the stability conditions. The pull-in ranges are examined numerically. The simulations are done in MATLAB, and it is shown that the linear range extension results in an extended pull-in range in both cases, but the initial condition of the loop filter affects the extended pull -in range for the second order loop.

IEEE2020