Ali Saeidi

Related publications (30)

Ferroelectric Junctionless Double-Gate Silicon-On-Insulator FET as a Tripartite Synapse

Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Sadegh Kamaei Bahmaei, Ali Saeidi, Igor Stolichnov

In this work, we report the concept and experimentally demonstrate the first tunable ferroelectric (Fe) junctionless (JL) transistor (Fe-JLFET), capable of emulating the functionality of biological tri-partite synapses, which is an artificial three-terminal synapse with unique back gate high tuning of the post-synaptic current (PSC). Our device consists of a double-gate 11nm-thin film Fe-JLFET with 10nm Si-doped HfO2 ferroelectric, mimicking the functionality of a tripartite synapse. The gradual ferroelectric switching is exploited to fully reproduce the synaptic plasticity. The back-gate voltage emulates the function of an astrocyte, being used to tune the synaptic weight by more than 400x. Compared to other implementations, the newly proposed tripartite Fe-JLFET synapse device shows simplicity in fabrication, extended programmability, and robustness. We report plasticity until 2000 cycles of operation. Overall, this device concept is promising for CMOS-compatible energy-efficient implementation of future neuromorphic ICs.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Negative Capacitance in HfO2 Gate Stack Structures With and Without Metal Interlayer

Francesco Bellando, Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Ali Saeidi, Igor Stolichnov

In this work, we experimentally explore and compare FET gate stacks with and without an inner metal plane between a linear dielectric (SiO2) and a ferroelectric layer (Si-doped HfO2) operating in the negative capacitance (NC) regime. The use of nanosecond-range pulses enables us to observe hysteresis-free NC and reconstruct the S-shaped polarization-voltage curves. The devices with the inner metal plate show a higher equivalent NC value, which offers the potential for a higher differential amplification in a NC-FET. However, such a NC region is observed over a smaller range of electric field and polarization, which leads to hysteresis. Moreover, the presence of a metal layer in between the ferroelectric and the insulator favors domain formation resulting in destabilization of the NC effect. For the gate structure where the ferroelectric and the insulator are in contact, the S-shaped polarization-voltage curve shows a better agreement with Landau-Ginzburg-Devonshire formalism for the monodomain state. The uniform polarization closely mimicking the monodomain state is possible due to the polarization imprint occurring due to the structural asymmetry. By nanometer resolution polarization mapping via off-resonance piezoelectric force microscopy (PFM), we corroborate the presence of imprint, which can intrinsically stabilize one ferroelectric state. Overall, the article provides an experimental demonstration that the absence of the inner metal plane in the gate structures stabilizes the NC regime favorable for hysteresis-free NC-FET.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures

Luca Capua, Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Sadegh Kamaei Bahmaei, Teodor Rosca, Ali Saeidi

We report the fabrication process and performance characterization of a fully integrated ferroelectric gate stack in a WSe2/SnSe2 Tunnel FETs (TFETs). The energy behavior of the gate stack during charging and discharging, together with the energy loss of a switching cycle and gate energy efficiency factor are experimentally extracted over a broad range of temperatures, from cryogenic temperature (77 K) up to 100 degrees C. The obtained results confirm that the linear polarizability is maintained over all the investigated range of temperature, being inversely proportional to the temperature T of the ferroelectric stack. We show that a lower-hysteresis behavior is a sine-qua-non condition for an improved energy efficiency, suggesting the high interest in a true NC operation regime. A pulsed measurement technique shows the possibility to achieve a hysteresis-free negative capacitance (NC) effect on ferroelectric 2D/2D TFETs. This enables sub-15 mV dec(-1) point subthreshold slope, 20 mV dec(-1) average swing over two decades of current, I-ON of the order of 100 nA mu m(-2) and I-ON/I-OFF > 10(4) at V-d = 1 V. Moreover, an average swing smaller than 10 mV dec(-1) over 1.5 decades of current is also obtained in a NC TFET with a hysteresis of 1 V. An analog current efficiency factor, up to 50 and 100 V-1, is achieved in hysteresis-free NC-TFETs. The reported results highlight that operating a ferroelectric gate stack steep slope switch in the NC may allow combined switching energy efficiency and low energy loss, in the hysteresis-free regime.

NATURE PORTFOLIO2021

Intrinsic switching in Si-doped HfO2: A study of Curie-Weiss law and its implications for negative capacitance field-effect transistor

Matteo Cavalieri, Carlotta Gastaldi, Mihai Adrian Ionescu, Sadegh Kamaei Bahmaei, Teodor Rosca, Ali Saeidi, Igor Stolichnov

HfO2-based ferroelectrics are considered a promising class of materials for logic and memory applications due to their CMOS compatibility and ferroelectric figures of merit. A steep-slope field-effect-transistor (FET) switch is a device for logic applications in which a ferroelectric gate stack exploits a stabilized negative capacitance regime capable to differentially amplify the surface potential in a metal-oxide-semiconductor FET structure, resulting in the improvement of the subthreshold swing and overdrive. In a number of relevant studies of negative capacitance, intrinsic (thermodynamic) switching is assumed, since alternative switching scenarios predict undesirable hysteretic responses in logic devices. However, there is little support from the experimental data showing that the polarization reversal in HfO2-based ferroelectrics is really driven by the intrinsic switching mechanism. In this work, polarization hysteresis loops are measured over wide temperature ranges on polycrystalline Si-doped HfO2 (Si:HfO2) capacitors. The analysis herein, which is based on the classic Landau-Ginzburg-Devonshire theory, yields the temperature-dependent dielectric susceptibility values, which fit the Curie-Weiss law. The extrapolated Curie temperature value is in line with the data obtained for other HfO2-based ferroelectrics using different techniques. The work also illustrates a method to evaluate the ferroelectric equivalent negative capacitance value and range of voltages, aiming at study and optimization of a stabilized negative capacitance FET. This study indicates that the intrinsic switching provides an adequate description of the polarization hysteresis in Si:HfO2 films. This confirms the usability of hafnia-based ferroelectrics for negative capacitance logic devices, and the important role that the intrinsic mechanism plays in the dielectric response of these materials.

AMER INST PHYSICS2021

An Experimental Study on Mixed-Dimensional 1D-2D van der Waals Single-Walled Carbon Nanotube-WSe2 Hetero-Junction

Matteo Cavalieri, Mihai Adrian Ionescu, Farzan Jazaeri, Sadegh Kamaei Bahmaei, Benjamin Paul Johanès Gabriel Lambert, Nicolò Oliva, Amin Rassekh, Ali Saeidi

This experimental study investigates a novel multi-functional one dimensional-two dimensional (1D-2D) heterojunction made of two different band-gap semiconductors, i.e. single-walled carbon nanotube (SWCNT) and tungsten di-selenide (WSe2). The proposed ultra-scaled van der Waals junction behaves like a p-type field-effect transistor (FET) or a gated p-n diode, depending upon the gate bias. A detailed physical study of charge transportation mechanism is presented in a wide range of applied potentials. The obtained results are important towards scaling nanoelectronics to atomic thicknesses by means of the 1D-2D hybrid junctions with additional multi-functional solid-state devices.

2020

Corrections to “Experimental Details of a Steep-Slope Ferroelectric InGaAs Tunnel-FET With High-Quality PZT and Modeling Insights in the Transient Polarization”

Mihai Adrian Ionescu, Hiroshi Iwai, Ali Saeidi, Igor Stolichnov

This correspondence highlights that the Gibbs free energy description of a ferroelectric capacitor in series with a paraelectric capacitor, depends on the initial charge on the plates of the ferroelectric capacitor. An incomplete Gibbs free energy description, as in the original manuscript, leads to an incorrect simulation result. Therefore, a fully comprehensive analytical description and a corrected conclusion concerning the particular point of an increase in apparent coercive voltage in the steep-slope ferroelectric tunnel-FET, are presented.

2020

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Matteo Cavalieri, Mihai Adrian Ionescu, Teodor Rosca, Ali Saeidi, Igor Stolichnov

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

AMER CHEMICAL SOC2020

Negative capacitance semiconductor sensor

Francesco Bellando, Mihai Adrian Ionescu, Ali Saeidi

The present invention relates to a semiconductor sensor (1) comprising: a source element (17, 19); a drain element (21, 23); a semiconductor channel element (25) between the source element (17, 19) and the drain element (21, 23) for forming an electrically conductive channel; a first insulator (27) between the semiconductor channel element and a solution (3) to be sensed; a reference electrode (9) configured to be in contact with the solution (3), the reference electrode (9) being configured to set an electric potential of the solution; a bias voltage source (5) for generating an external sensor bias voltage for electrically biasing the reference electrode (9); and a sensing surface (27, 37) for interacting with the solution (3) comprising analytes for generating a surface potential change at the sensing surface dependent on the concentration of the analytes in the solution. The sensor further comprises a ferroelectric capacitance element (7) between the first insulator (27) and the bias voltage source (5) for generating a negative capacitance for providing a differential gain between the external sensor bias voltage and an internal sensor bias voltage sensed at a surface of the channel element (25) facing the first insulator (27) or ferroelectric capacitance element (7).

2020

Subthermionic negative capacitance ion sensitive field-effect transistor

Francesco Bellando, Carlotta Gastaldi, Mihai Adrian Ionescu, Ali Saeidi

One of the main advantages of Ion-Sensitive Field-Effect Transistor (ISFET) technology is the capability to exploit technological advancements initially developed for conventional FETs for logic applications, such as the employ of high-k dielectrics for the gate and the definition of fully depleted and gate all around structures. Negative Capacitance (NC) is an emerging concept exploiting ferroelectric materials integrated in field effect transistor gate stacks in order to decrease their subthreshold swing and improve the drain current (I-D) overdrive in order to reach more energy efficient devices, operated at lower voltage. In this work, we investigate and experimentally demonstrate the application of this concept to enable subthermionic ISFETs with enhanced current sensitivity and low power operation. A physical model for the introduced NC ISFET is presented and optimized by fitting of the experimental results, providing further insights into the sensor parameters and a predictive tool for the design of future NC-based sensors.

2020

Experimental Details of a Steep-Slope Ferroelectric InGaAs Tunnel-FET With High-Quality PZT and Modeling Insights in the Transient Polarization

Mihai Adrian Ionescu, Hiroshi Iwai, Ali Saeidi, Igor Stolichnov

The steep-slope ferroelectric tunnel-FET (SS-FeTFET), consisting of an InGaAs TFET with a sub-60 mV/dec subthreshold swing (SS) at room temperature and an externally connected high-quality single-crystalline PZT capacitor, displays improved SS compared to the standalone TFET. In this article, we describe the measurement procedure and measurement results of this SS-FeTFET in great detail. To quantitatively extract the ferroelectric (FE) polarization during voltage sweeps, device simulations of the TFET are combined with the SS-FeTFET measurement results. Finally, qualitative insight in some peculiarities of the experimental observations is given, such as the apparent coercive voltage that is larger in the SS-FeTFET than in the standalone FE, the shape of the polarization during voltage sweeps, and the small polarization hysteresis loop at voltages close to the apparent coercive voltage.

2019