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Simulation of Double-Gate Silicon Tunnel FETs with a High-k Gate Dielectric

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Explicit drain current model of junctionless double-gate field-effect transistors

Jean-Michel Sallese, Ashkhen Yesayan

This paper presents an explicit drain current model for the junctionless double-gate metal-oxide-semiconductor field-effect transistor. Analytical relationships for the channel charge densities and for the drain current are derived as explicit functions of ...

Pergamon-Elsevier Science Ltd2013

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Jean-Michel Sallese, Farzan Jazaeri, Adil Koukab, Lucian Barbut

In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along ...

Elsevier2013

Downscaling and Short Channel Effects in Twin Gate Junctionless Vertical Slit FETs

Jean-Michel Sallese, Didier Bouvet, Farzan Jazaeri, Lucian Barbut

we present the performance constraints in the design of ultra-thin body Junctionless Vertical Slit Field Effect Transistor (JL VeSFET). A design space that take into account the intrinsic off-current, the sub-threshold swing and the drain induced barrier l ...

2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

From All-Si Nanowire TFETs Towards III-V TFETs

Hesham Ghoneim

Performance improvement by device scaling has been the prevailing method in the semiconductor industry over the past four decades. However, current silicon transistor technology is approaching a fundamental limit where scaling does not improve device perfo ...

EPFL2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

On the Static and Dynamic Behavior of the Germanium Electron-Hole Bilayer Tunnel FET

Mihai Adrian Ionescu, Luca De Michielis, Livio Lattanzio, Nilay Dagtekin

Tunnel FETs (TFETs) are being intensively investigated for their potential in achieving subthermal switching slopes and extremely low leakage currents. Recently, a promising concept has been proposed: the electron-hole bilayer TFET (EHBTFET), which exploit ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Tri-Gate Normally-Off GaN Power MISFET

Elison de Nazareth Matioli, Bin Lu

We present a new normally-off GaN transistor-the tri-gate normally-off GaN metal-insulator-semiconductor field-effect transistor (MISFET). Due to the excellent channel control of a new 3-D gate structure, a breakdown voltage of 565 V has been achieved at a ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Breakdown of High-Performance Monolayer MoS2

Andras Kis, Dominik Sebastian Lembke

Two-dimensional (2D) materials such as monolayer molybdenum disulfide (MoS2) are extremely interesting for integration in nanoelectronic devices where they represent the ultimate limit of miniaturization in the vertical direction. Thanks to the presence of ...

Amer Chemical Soc2012

The electron–hole bilayer tunnel FET

Mihai Adrian Ionescu, Luca De Michielis, Livio Lattanzio

We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher driv ...

Elsevier2012