Publication

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Related publications (50)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

Graph Chatbot

Chat with Graph Search

Towards Multi-Fabric 3D Integration Architectures

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

3D Integration Technology for Lab-on-a-Chip Applications

A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory

Towards Cost Effective Multi-Core Processor Platforms Using 3-D Stacking Technology

Hierarchical Thermal Management Policy for High-Performance 3D Systems with Liquid Cooling

Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

3D Thermal-Aware Floorplanner for Many-Core Single-Chip Systems

Parallel Programmable Asynchronous Neighborhood Mechanism for Kohonen SOM Implemented in CMOS Technology