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Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

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Impact of Data Serialization over TSVs on Routing Congestion in 3D-Stacked Multi-Core Processors

Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Giulia Beanato

3D integration can alleviate routing congestion, reducing the wirelength and improving performances. Nevertheless, each TSV still occupies non-negligible silicon area: as the number of TSV increases, their effect on the chip routing is detrimental. The red ...

Elsevier2016

Memory Systems and Interconnects for Scale-Out Servers

Stavros Volos

The information revolution of the last decade has been fueled by the digitization of almost all human activities through a wide range of Internet services. The backbone of this information age are scale-out datacenters that need to collect, store, and proc ...

EPFL2015

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Giovanni De Micheli, Luca Benini

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and l ...

Institute of Electrical and Electronics Engineers2015

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

2014

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In this work, a chip-level post-CMOS processing protocol for 3D integration is presented to achieve multilayer stacking. This protocol includes TSV formation on the top chip, bonding the chips on top of each other, and finally the electrical connection pro ...

2014

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Two diverse manufacturing techniques for building 3-D integrated systems are vertical integration with Through-Silicon-Vias (TSVs), also referred to as 3-D TSV integration, and 3-D monolithic integration. In this paper, we present a hybrid integration sche ...

2013

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This paper presents a chip-level postcomplementary metal oxide semiconductor (CMOS) processing technique for 3-D integration and through-silicon-via (TSV) fabrication. The proposed technique is based on dry-film lithography, which is a low-cost and simple ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Integration of Intra Chip Stack Fluidic Cooling using Thin-Layer Solder Bonding

John Richard Thome, Michail Zervas, Yusuf Leblebici, Yassir Madhour, Bruno Michel

Three-dimensional (3D) stacking of integrated circuit (IC) dies by vertical integration increases system density and package functionality. The vertical integration of IC dies by area-array Through-Silicon-Vias (TSVs) reduces the length of global interconn ...

IEEE2013

Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache

Babak Falsafi, Stavros Volos

Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories — block-based and page-based. The former organize data in conventional blocks (e.g., 64B), ensurin ...

ACM2013

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Microfabricated electrospray thrusters are widely acknowledged as one of the most promising technologies for the propulsion of small spacecraft. Their relative simplicity, high efficiency (> 70%), low footprint (M < 500g, V < 10cm3) and large potential spe ...

2013