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Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

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Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

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Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

Methods and systems for power-efficient inductive chip-to-chip communications

Manycore Network Interfaces for In-Memory Rack-Scale Computing

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Design of Digital SoC for Operation at High Temperatures

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Flip-chip integration of Si bare dies on polymeric substrates at low temperature using ICA vias made in dry film photoresist

ICCAD 2015 Contest in 3D Interlayer Cooling Optimized Network

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

A Die-Level Post-CMOS Processing Protocol for Multi-Layer 3D Integration

Design of Digital SoC for Operation at High Temperatures

Manycore Network Interfaces for In-Memory Rack-Scale Computing

Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Low Power 3D Serial TSV Link for High Bandwidth Cross-Chip Communication

Methods and systems for power-efficient inductive chip-to-chip communications