Publication

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Related publications (48)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

A 35mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32nm Digital SOI CMOS

Graph Chatbot

Chat with Graph Search

Comparison of Different Precision Pseudo Resistor Realizations in the DC-Feedback of Capacitive Transimpedance Amplifiers

Design techniques for a stable operation of cryogenic field-programmable gate arrays

A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems

Virtual Submodule Concept for Fast Semi-Numerical Modular Multilevel Converter Loss Estimation

High frequency self-oscillating current switching for a fully integrated fail-safe stimulator output stage

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A Fully Integrated Counter Flow Energy Reservoir for Peak Power Delivery in Small Form-Factor Sensor Systems

Virtual Submodule Concept for Fast Semi-Numerical Modular Multilevel Converter Loss Estimation

Comparison of Different Precision Pseudo Resistor Realizations in the DC-Feedback of Capacitive Transimpedance Amplifiers

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

Design techniques for a stable operation of cryogenic field-programmable gate arrays

A 110mW 6 Bit 36GS/S Interleaved SAR ADC for 100 GBE Occupying 0.048mm2 in 32nm SOI CMOS

High frequency self-oscillating current switching for a fully integrated fail-safe stimulator output stage

Design of an integrated thermoelectric generator power converter for ultra-low power and low voltage body energy harvesters aimed at ExG active electrodes

A 5.9mW/Gb/s 7Gb/s/pin 8-Lane Single-Ended RX with Crosstalk Cancellation Scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS