Publication

Junctionless silicon nanowire transistors for the tunable operation of a highly sensitive, low power sensor

Related publications (61)

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

This paper presents analytical expressions for channel noise, induced gate noise (IGN), and cross-correlation noise in a long-channel junctionless (JL) double-gate MOSFET. The analytical relationships, which have been derived from a coherent charge-based m ...

Ieee-Inst Electrical Electronics Engineers Inc2015

Assessment of Pseudo-Bilayer Structures in the Heterogate Germanium Electron-Hole Bilayer Tunnel Field-Effect Transistor

Mihai Adrian Ionescu, Cem Alper, José Luis Padilla de la Torre

We investigate the effect of pseudo-bilayer configurations at low operating voltages (

American Institute of Physics2015

Trans-Capacitance Modeling in Junctionless Gate-All-Around Nanowire FETs

Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut

In this letter, we derive an analytical model for trans-capacitances in Junctionless Nanowire Field Effect Transistors (JL NW FET). As for static operation, we show that a complete small signal capacitance network can be built upon an equivalence scheme re ...

Elsevier2014

Junctionless nano-electro-mechanical resonant transistor

Mihai Adrian Ionescu, Sebastian Thimotee Bartsch

A junctionless Nano-Electro-Mechanical (NEM) resonator, comprising a highly doped conductive channel (4) connecting a drain (9) and a source (10) electrode and movably fixed by at least two ends (11, 11') acting as said source and drain electrodes, respect ...

2014

High Sensitive Detection in Tumor Extracts with SiNW-FET in-Air Biosensors

Giovanni De Micheli, Sandro Carrara, Francesca Puppo

We have already demonstrated that high quality SiNW-FETs can be used to sense very low concentration range (fM) of pathogenic factors in controlled PBS. In this work we show, for the first time, Silicon Nanowire Field Effect Transistors (SiNW-FET) as biose ...

IEEE2014

Design Methodologies and CAD for Emerging Nanotechnologies

Shashi Kanth Bobba

With technology scaling reaching the fundamental limits of Si-CMOS in the near future, the semiconductor industry is in quest for innovation from various disciplines of integrated circuit (IC) design. At a fundamental level, technology forms the main drive ...

EPFL2013

Single-layer MoS₂

Branimir Radisavljevic

This thesis explores the electronic properties of one layered transition-metal dichalcogenide – single-layer MoS2, and demonstrates the first transistors and integrated circuits with characteristics that outperform graphene electronics in many aspects and ...

EPFL2013

Mobility Extraction Assessment in GAA Si NW JL FETs with Cross-Section Down to 5 nm

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first ...

IEEE2013

Transient Off-Current in Junctionless FETs

Jean-Michel Sallese, Didier Bouvet, Farzan Jazaeri, Lucian Barbut

We report preliminary measurements of transient drain current undershoot with time constants of the order of milliseconds in thick and highly doped n-type junctionless fieldeffect transistors. This effect might be attributed to a process involving generati ...

Ieee-Inst Electrical Electronics Engineers Inc2013

Design and modeling of self-aligned nano-imprinted sub-micrometer pentacene-based organic thin-film transistors

Christian Enz, Jean-Michel Sallese, Rolando Ferrini, Randoald Müller, Nenad Marjanovic, Frédéric Zanella

Sub-micrometer channel length (0.5 mu m) organic thin-film transistors (OTFTs) are demonstrated using a process flow combining nano-imprint lithography (NIL) and self-alignment (SA). A dedicated test structure was designed and samples were fabricated on 4- ...

Elsevier2013

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