Publications related to FireBird: PowerPC e200 Based SoC for High Temperature Operation

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

A programmable patient-customized epileptic seizure detector is proposed in this paper to enable neurologists and patients to have constructive interactions with the implantable medical device. The programmability feature is enabled by designing a low-powe ...

IEEE2023

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

Andreas Peter Burg, Reza Ghanaatian Jahromi, Marco Widmer

This article presents a design-for-test methodology for embedded memories. The methodology relies on a fully random fault model of post-fabrication errors, which results in a low-overhead test strategy. The methodology's effectiveness is demonstrated on an ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Mohamed Mostafa Sabry Aly, Halima Najibi

Deeply-scaled three-dimensional (3D) Multi-Processor Systems-on-Chip (MPSoCs) enable high performance and massive communication bandwidth for next-generation computing. However, as process nodes shrink, temperature-dependent leakage dramatically increases, ...

2020

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

Andreas Peter Burg, David Ruffieux

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

IEEE2019

A machine learning approach for power gating the FPGA routing network

Mirjana Stojilovic, Hossein Asadi

Power gating is a common approach for reducing circuit static power consumption. In FPGAs, resources that dominate static power consumption lie in the routing network. Researchers have proposed several heuristics for clustering multiplexers in the routing ...

IEEE COMPUTER SOC2019

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC

Andreas Peter Burg, David Ruffieux

In this paper, we describe a systematic low-power design methodology for technologies that offer a strong body factor. Specifically, we explore both the body bias voltage and the supply voltage knobs in order to find the MEP (minimum energy point) for a co ...

IEEE2019

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Edoardo Charbon, Harald Arjan Robert Homulle

In this paper, we show how a deep-submicron field-programmable gate array (FPGA) can be operated more stably at extremely low temperatures through special firmware design techniques. Stability at low temperatures is limited through long power supply wires ...

2018

A 32kHz crystal oscillator leveraging voltage scaling in an ultra-low power 40nA real-time clock

Maher Kayal, François Krummenacher, Mathieu Yves Hervé Coustans

In this paper, an ultra-low power consumption crystal oscillator embedded in an RTC module (ASIC and its crystal resonator) is presented. The technique leverages oscillation amplitude and loads capacitance scaling; it incorporates transistor level merging ...

IEEE2018

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FireBird: PowerPC e200 Based SoC for High Temperature Operation

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

A machine learning approach for power gating the FPGA routing network

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC

Design techniques for a stable operation of cryogenic field-programmable gate arrays

A 32kHz crystal oscillator leveraging voltage scaling in an ultra-low power 40nA real-time clock

Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

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Chat with Graph Search

Towards Deeply Scaled 3D MPSoCs with Integrated Flow Cell Array Technology

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

A Real-Time Multi-Camera Depth Estimation ASIC with Custom On-Chip Embedded DRAM

Programmable Seizure Detector Using a 32-bit RISC Processor for Implantable Medical Devices

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

A machine learning approach for power gating the FPGA routing network

Design techniques for a stable operation of cryogenic field-programmable gate arrays

Modeling and optimization of Tunnel-FET architectures exploiting carrier gas dimensionality

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC

A 32kHz crystal oscillator leveraging voltage scaling in an ultra-low power 40nA real-time clock