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pH Response of Silicon Nanowire Sensors: Impact of Nanowire Width and Gate Oxide

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Silicon–germanium

SiGe (ˈsɪɡiː or ˈsaɪdʒiː), or silicon–germanium, is an alloy with any molar ratio of silicon and germanium, i.e. with a molecular formula of the form Si1−xGex. It is commonly used as a semiconductor material in integrated circuits (ICs) for heterojunction bipolar transistors or as a strain-inducing layer for CMOS transistors. IBM introduced the technology into mainstream manufacturing in 1989. This relatively new technology offers opportunities in mixed-signal circuit and analog circuit IC design and manufacture.

Silicon on sapphire

Silicon on sapphire (SOS) is a hetero-epitaxial process for metal–oxide–semiconductor (MOS) integrated circuit (IC) manufacturing that consists of a thin layer (typically thinner than 0.6 μm) of silicon grown on a sapphire (Al2O3) wafer. SOS is part of the silicon-on-insulator (SOI) family of CMOS (complementary MOS) technologies. Typically, high-purity artificially grown sapphire crystals are used. The silicon is usually deposited by the decomposition of silane gas (SiH4) on heated sapphire substrates.

Self-aligned gate

In semiconductor electronics fabrication technology, a self-aligned gate is a transistor manufacturing approach whereby the gate electrode of a MOSFET (metal–oxide–semiconductor field-effect transistor) is used as a mask for the doping of the source and drain regions. This technique ensures that the gate is naturally and precisely aligned to the edges of the source and drain. The use of self-aligned gates in MOS transistors is one of the key innovations that led to the large increase in computing power in the 1970s.

CMOS

Complementary metal–oxide–semiconductor (CMOS, pronounced "sea-moss", siːmɑːs, -ɒs) is a type of metal–oxide–semiconductor field-effect transistor (MOSFET) fabrication process that uses complementary and symmetrical pairs of p-type and n-type MOSFETs for logic functions. CMOS technology is used for constructing integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS), and other digital logic circuits.

Fast Ethernet

In computer networking, Fast Ethernet physical layers carry traffic at the nominal rate of 100 Mbit/s. The prior Ethernet speed was 10 Mbit/s. Of the Fast Ethernet physical layers, 100BASE-TX is by far the most common. Fast Ethernet was introduced in 1995 as the IEEE 802.3u standard and remained the fastest version of Ethernet for three years before the introduction of Gigabit Ethernet. The acronym GE/FE is sometimes used for devices supporting both standards.

Logic gate

A logic gate is an idealized or physical device that performs a Boolean function, a logical operation performed on one or more binary inputs that produces a single binary output. Depending on the context, the term may refer to an ideal logic gate, one that has, for instance, zero rise time and unlimited fan-out, or it may refer to a non-ideal physical device (see ideal and real op-amps for comparison). In the real world, the primary way of building logic gates uses diodes or transistors acting as electronic switches.

XOR gate

XOR gate (sometimes EOR, or EXOR and pronounced as Exclusive OR) is a digital logic gate that gives a true (1 or HIGH) output when the number of true inputs is odd. An XOR gate implements an exclusive or () from mathematical logic; that is, a true output results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequality function, i.e., the output is true if the inputs are not alike otherwise the output is false.

65 nm process

The 65 nm process is an advanced lithographic node used in volume CMOS (MOSFET) semiconductor fabrication. Printed linewidths (i.e. transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm. For comparison, cellular ribosomes are about 20 nm end-to-end. A crystal of bulk silicon has a lattice constant of 0.543 nm, so such transistors are on the order of 100 atoms across. By September 2007, Intel, AMD, IBM, UMC and Chartered were also producing 65 nm chips.

10 Gigabit Ethernet

10 Gigabit Ethernet (abbreviated 10GE, 10GbE, or 10 GigE) is a group of computer networking technologies for transmitting Ethernet frames at a rate of 10 gigabits per second. It was first defined by the IEEE 802.3ae-2002 standard. Unlike previous Ethernet standards, 10GbE defines only full-duplex point-to-point links which are generally connected by network switches; shared-medium CSMA/CD operation has not been carried over from the previous generations of Ethernet standards so half-duplex operation and repeater hubs do not exist in 10GbE.

Insulated-gate bipolar transistor

An insulated-gate bipolar transistor (IGBT) is a three-terminal power semiconductor device primarily forming an electronic switch. It was developed to combine high efficiency with fast switching. It consists of four alternating layers (P–N–P–N) that are controlled by a metal–oxide–semiconductor (MOS) gate structure. Although the structure of the IGBT is topologically similar to a thyristor with a "MOS" gate (MOS-gate thyristor), the thyristor action is completely suppressed, and only the transistor action is permitted in the entire device operation range.