Publication

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Related publications (129)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Graph Chatbot

Chat with Graph Search

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding

A Current Sensing Completion Detection Method for Asynchronous Pipelines Operating In the Sub-threshold Regime

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

A 16-bit, 150-μW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme

A Low Power Current-Mode Binary-Tree WTA / LTA Circuit for Kohonen Neural Networks

A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

Lukasiewicz Fuzzy Logic Networks and Their Ultra Low Power Hardware Implementation

Fault-Tolerance and Reliability of Post-CMOS Systems: a Circuit Perspective

A Current Sensing Completion Detection Method for Asynchronous Pipelines Operating In the Sub-threshold Regime

Improving Power-Delay Performance of Ultra Low-Power Subthreshold SCL Circuits

A Low Power Current-Mode Binary-Tree WTA / LTA Circuit for Kohonen Neural Networks

Lukasiewicz Fuzzy Logic Networks and Their Ultra Low Power Hardware Implementation

A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

Subthreshold Leakage Reduction: A Comparative Study of SCL and CMOS Design

Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-Vt Domain By Architectural Folding

A 16-bit, 150-μW, 1-kS/s ADC with hybrid incremental and cyclic conversion scheme

A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

Fault-Tolerance and Reliability of Post-CMOS Systems: a Circuit Perspective