Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs
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Integrated circuit (1) comprising: an array of single photon avalanche diodes (SPADs), a plurality of read-out circuits, each SPADs being coupled to one read-out circuit, wherein at least some of the read-out circuits comprise time-to-digital converters (T ...
This research work deals with the design of linear CMOS RF power amplifiers. Two important aspects are treated: efficiency enhancement and frequency-tunable capability. For this purpose, two different integrated circuits were realized in a 0.11 µm technolo ...
Integrated circuit (1) comprising: an array of single photon avalanche diodes (SPADs), a plurality of read-out circuits, each SPADs being coupled to one read-out circuit, wherein at least some of the read-out circuits comprise time-to-digital converters (T ...
This paper presents a fully integrated remotely powered and addressable radio frequency identification (RFID) transponder working at 2.45 GHz. The achieved operating range at 4 W effective isotropically radiated power (EIRP) base-station transmit power is ...
Radiation detectors based on the deposition of a 10 to 30 μm thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time i ...
The prospective use of upcoming nanometer CMOS technology nodes (65nm, 45nm, and beyond) in bio-electronic interfaces is raising a number of important issues concerning circuit architectures and design. In particular, the advantages of scaling and higher d ...
Recently, artificial intelligence (AI) systems gain an increasing popularity and their development is fast. One of the most important fields of the AI system development are artificial neural networks (ANN’s) which, due to continuous progress in microelect ...
One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the ...
Information processing with only locally connected networks such as cellular neural networks is advantageous for integrated circuit implementations. Adding long range connections can often enhance considerably their performance. It is sufficient to activat ...
The quickening pace of the MOSFET technology scaling has pushed the MOSFET dimension towards 10 nanometer channel length, where it is going to face the following fundamental and performance limiting factors: (i) electrostatic limits, (ii) source to drain t ...