Publication

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Related publications (53)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

High-Voltage Tolerant Bi-State Self-Biasing Output Driver using Cascade Complementary Latches in Twin-well CMOS Technology

Graph Chatbot

Chat with Graph Search

Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process

DRAM Based on Hysteresis in Impact Ionization Single-Transistor-Latch

Subthreshold Source-Coupled Logic Circuits for Ultra Low Power Applications

Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage

Current mode Alalog Kohonen Neural Network

Ultra-thin nanograin polysilicon devices for hybrid CMOS-NANO integrated circuits

A Power-Efficient LVDS Driver Circuit in 0.18-um CMOS Technology

A fast Modulator for dynamic supply linear RF power amplifier

CMOS Current Steering Logic: Toward a matured technique for mixed-mode applications

Design guidelines for CMOS current steering logic