A DAC Assisted Speed Enhancement Technique for High Resolution SAR ADC
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We propose an analog-to-digital converter (ADC) architecture, implemented in an FPGA, that is fully reconfigurable and easy to calibrate. This approach allows to alter the design, according to the system requirements, with simple modifications in the firmw ...
A model for voltage-based time-interleaved sampling is introduced with two implementations of highly interleaved analog-to-digital converters (ADCs) for 100 Gb/s communication systems. The model is suitable for ADCs where the analog input bandwidth is of c ...
A technique for the calibration of DAC (digital to analog converter) mismatch errors in multi-bit Sigma Delta modulators (SDM) is presented. It consists of two parts: the first is a measurement technique to obtain the relative mismatch of each feedback DAC ...
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and theref ...
This paper presents the design of a dual-channel 4-bit analog-to-digital converter (ADC) for the sub-sampling impulse radio ultra-wideband receiver with the sampling rate of 2.112 GS/s. The ADC's specifications are optimized at the system level. Two parall ...
This thesis describes a novel digital background calibration scheme for pipelined ADCs with nonlinear interstage gain. Errors caused by the nonlinear gains are corrected in real-time by adaptively post-processing the digital stage outputs. The goal of this ...
In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used as a sampling clock to an analog-to-digital converter (ADC), it creates spurious sidebands in the sampled data a ...
The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are t ...
The long-standing analog-to-digital conversion paradigm based on Shannon/Nyquist sampling has been challenged lately, mostly in situations such as radar and communication signal processing where signal bandwidth is so large that sampling architectures cons ...
Clock timing jitter refers to random perturbations in the sampling time in analog-to-digital converters (ADCs). The perturbations are caused by circuit imperfections in the sampling clock. This paper analyzes the effect of sampling clock jitter on the acqu ...