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Design Techniques for Ultra High Frequency Clock Generation in 28 nm FDSOI Technology

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An Analytical Model of Hardware Transactional Memory

Willy Zwaenepoel, Paolo Romano, Diego Didona

This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in ...

2017

A Hybrid CDAC-Threshold Configuring SAR ADC in 28nm FDSOI CMOS

Mustafa Kilic, Yusuf Leblebici, Themistoklis Mavrogordatos

In this paper, a 9-bit 1.3 GS/s single channel SAR ADC is presented. In conventional SAR ADCs, the capacitive DAC size grows exponentially with respect to converter resolution. This results in both signal bandwidth and conversion speed reduction. The propo ...

2017

The design of Wren, a Fast and Scalable Transactional Causally Consistent Geo-Replicated Key-Value Store

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

This paper presents the design of Wren, a new geo-replicated key-value store that achieves Transactional Causal Consistency. Wren leverages two design choices to achieve higher performance and better scalability than existing systems. First, Wren uses hybr ...

2017

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Denis Sallin

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses ...

EPFL2016

This paper presents a frequency synthesizer based on a phase locked loop (PLL) targeting low jitter applications. The frequency generator covers a range wider than a decade, more explicitly from 20 to 300 MHz. Thanks to a 4-stage ring oscillator, it can pr ...

Ieee2016

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Seyed Armin Tajalli, Yusuf Leblebici, Kiarash Gharibdoust

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the referenc ...

Ieee2016

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...

EPFL2015

Reducing Energy Dissipation in ULP Systems: PLL-Free FBAR-Based Fast Startup Transmitters

Christian Enz, David Ruffieux, Raghavasimhan Thirunarayanan

The energy dissipated by conventional phase-locked-loop-based transmitters (TXs) during the long startup phase is a major bottleneck that reduces the energy autonomy of duty-cycled ultra-low-power systems. In order to tackle this problem, this paper presen ...

Institute of Electrical and Electronics Engineers2015

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System and methods for producing a plurality of Sinc shaped pulses in the time domain include a light source for providing an input light signal having an input frequency, and at least one spectrum shaper for producing the plurality of Sinc shaped pulses f ...

United States Patent and Trademark Office2015

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2015