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A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Related publications (123)

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Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

In this study, design considerations for ultra low voltage (ULV) standard-cell based memories (SCM) are presented. Trade-offs for area cost, leakage power, access time, and access energy are discussed and realized using different read logic styles, latch a ...

Institute of Electrical and Electronics Engineers2016

Cmos image sensor

Assim Boukhayma, Arnaud Peizerat

A CMOS image sensor including a pixel including: a photodiode in series with a MOS transistor between a first reference potential and a sense node; a MOS transistor connecting the sense node to a second reference potential; and a third MOS transistor assem ...

2016

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Denis Sallin

During the last decades, the usage of silicon photodetectors, both as stand-alone sensor or integrated in arrays, grew tremendously. They are now found in almost any application and any market range, from leisure products to high-end scientific apparatuses ...

EPFL2016

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Christian Enz, Pierre-André Farine, Cyril Botteron, Gabriele Tasselli

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different juncti ...

Institute of Electrical and Electronics Engineers2016

Technology of integrated self-aligned E/D-mode n(++)GaN/InAlN/AlN/GaN MOS HEMTs for mixed-signal electronics

Nicolas Grandjean, Jean-François Carlin

We describe the technology and performance of integrated enhancement/depletion (E/D)-mode n(++) GaN/InAlN/AlN/GaN HEMTs with a self-aligned metal-oxide-semiconductor (MOS) gate structure. An identical starting epi-structure was used for both types of devic ...

Iop Publishing Ltd2016

Performance of Indium Gallium Zinc Oxide Thin-Film Transistors in Saline Solution

Stéphanie Lacour

Transistors are often envisioned as alternative transducing devices to microelectrodes to communicate with the nervous system. Independently of the selected technology, the transistors should have reliable performance when exposed to physiological conditio ...

Springer Verlag2016

One Transistor Active Pixel Sensor with Tunnel FET

Mihai Adrian Ionescu, Nilay Dagtekin

A tunneling field effect transistor for light detection, including a p-type region connected to a source terminal, a n-type region connected to a drain terminal, an intrinsic region located between the p-type region and the n-type region to form a P-I junc ...

2016

Flexible ultrathin-body single-photon avalanche diode sensors and CMOS integration

Edoardo Charbon

We proposed the world’s first flexible ultrathin-body single-photon avalanche diode (SPAD) as photon counting device providing a suitable solution to advanced implantable bio-compatible chronic medical monitoring, diagnostics and other applications. In thi ...

2016

Polarity Control at Runtime

Michele De Marchi

Semiconductor device research for digital circuit design is currently facing increasing challenges to enhance miniaturization and performance. A huge economic push and the interest in novel applications are stimulating the development of new pathways to ov ...

EPFL2015

Practical Applications of Tunnel Field Effect Transistors

Traditional metal-oxide-semiconductor field effect transistor scaling has advanced successfully over 50 years providing significant increases in transistor count per chip and operating frequency, thus enabled the built of ever more performant and complex s ...

EPFL2015