Fundamental aspects to localize self-catalyzed III-V nanowires on silicon

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2019
Journal paper

Abstract

III-V semiconductor nanowires deterministically placed on top of silicon electronic platform would open many avenues in silicon-based photonics, quantum technologies and energy harvesting. For this to become a reality, gold-free site-selected growth is necessary. Here, we propose a mechanism which gives a clear route for maximizing the nanowire yield in the self-catalyzed growth fashion. It is widely accepted that growth of nanowires occurs on a layerby-layer basis, starting at the triple-phase line. Contrary to common understanding, we find that vertical growth of nanowires starts at the oxide-substrate line interface, forming a ring-like structure several layers thick. This is granted by optimizing the diameter/height aspect ratio and cylindrical symmetry of holes, which impacts the diffusion flux of the group V element through the well-positioned group III droplet. This work provides clear grounds for realistic integration of III-Vs on silicon and for the organized growth of nanowires in other material systems.

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Growth mechanisms of III-V semiconductor nanostructures on silicon

Eleonora Russo

The aim of this thesis is to understand the dynamics of the growth of catalyst-free III-V semiconductor nanostructures on silicon substrates, focusing the attention mainly on the early stages of growths. A detailed understanding of this first phase of the process is a key step to obtain a completely successful integration of highly functional materials, like the III-Vs, on the CMOS platform, and to synthesize nanostructures with tailored properties. Indeed, the first mandatory step in nanotechnology is the possibility to fabricate nanostructures and nanomaterials, i.e. structures and materials with at least one dimension falling in the nanometer scale. Among different nanostructures, semiconductor nanowires (NWs) have proven to be versatile building blocks for a manifold of applications. In this work two types of nanostructures have been investigated: NWs and V-shaped nanomembranes. Their growth has been performed by molecular beam epitaxy (MBE), a technique that allows to produce ultrapure nanostructures, with very high crystalline quality and atomically sharp interfaces. The growth has been obtained with a self-catalyzed approach, meaning that no external material, apart the constituents of the semiconductor to be grown, has been used. This allows to avoid any possible contamination of the substrate, a fundamental requirement to ensure a full compatibility with the silicon technology. We performed a systematic study on the growth directions of self-catalyzed GaAs NWs grown on silicon substrates. Indeed, when growing III-V NWs on silicon non vertical wires always appear. In order to make NW-based structures on silicon effective for applications like energy harvesting (one of the most promising so far) it is mandatory to control the growth direction and in particular to maximize the yield of NWs perpendicular to the surface. By analyzing the first stages of growth we shed light on the mechanism responsible for the different NWs orientations: we optimized the growth conditions to obtain up to a 100% yield of vertical NWs. Having attained growth of nanostructures in an ordered manner along regular arrays is a subsequent step for the fabrication of devices. In this work our capability to control growth of InAs and GaAs NWs in arrays is presented and the existing challenges for the reproducible growth are highlighted. Lastly, we turned to the growth of nanostructures on exactly oriented (001) substrates, which would make the III-V/group IV integration compatible with the current technological pro- cesses. This led us to the discovery of a new class of III-V semiconductor nanostructures, called V-shaped nanomembranes, characterized by a unique morphology and growth mech- anism and possessing interesting optical properties. An accurate characterization of their morphology and a complete understanding of their nucleation and growth mechanism is reported. These results give a clear pathway of how to obtain fully controlled structures which as such could be useful for the realization of complex branched interconnected nanoelectronic devices.

EPFL2015

Silicon is today the main material used in electronics. It is a very advanced and mature technology. It is therefore clear that new technological concepts and materials should be introduced through the integration on the silicon platform. III-V semiconductors, such as GaAs and InAs, are high performance semiconductors, with direct bandgap and high carrier mobility, what makes them very prominent candidates for future electronics and optoelectronics. Lattice, thermal and polarity mismatch have been for decades limiting their integration on Si in the form of thin film technology. The nanowire geometry brings new prospects in this direction by reducing the contact area between mismatched materials,. Now, while growth of defect-free III-V structures on silicon is important, use in applications requires the nanostructures to be placed deterministically following a certain design/order. In this thesis we have studied different mechanisms to obtain ordered nanostructures on a silicon substrate, with the goal of increasing its functionality. The core part of this work was dedicated to the integration of III-V nanowires on Si in the formof ordered arrays. We have considered both GaAs and InAs nanowires. This process has several requirements: substrate fabrication and the growth process should be CMOS compatible, nanowires within the arrays should be grown vertically with a yield close to 100% and nanowires should be clones-looking and performing the same. An additional point to consider is that the fabrication process should be compatible with large scale techniques. The substrate requirements for obtaining ordered arrays of Ga-assisted GaAs nanowires on silicon were identified. In particular, we focused on the initial stages of growth, that turned to be key for achieving a high yield in the arrays. We found that the positioning of the Ga droplet within the predefined holes on the substrate determined whether the nanowire would grow perpendicularly to the substrate. Our HRTEMstudies on the titled nanowires show that the initial nanowire seeds seem to nucleate at the corner of the nanoscale holes. Instead, the crystal seeds of vertical nanowires occupy homogeneously the nanoscale holes. Achieving high yield in the growth of GaAs arrays on silicon also allowed us to study their evolution in time. We demonstrated that there is an incubation time for nanowires to start growing. This incubation time is different from NW to NWand leads to a relatively broad length distribution. We proposed a solution and showed how an increase in the supersaturation in the Ga droplet leads to the formation of homogeneous arrays. Growth of InAs nanowires in ordered arrays on silicon was based on the concept of guided growth. We used a SiO2 nanotube templates to promote vertical growth. Due to the directionality of MBE, achieving growth inside a nanotube was especially challenging. Our results provided new insights on the role of different pathways of the In and As4 adatoms during growth. In this part, large scale patterning by phase shift photolithography was demonstrated as an alternative to the conventionally used electron beam lithography. Stain etching method for producing porous silicon was applied on top-bottom fabricated Si micropillars. This led to geometrically driven electrochemical dissolution of silicon trough the center of the microstructure forming microtubes. The optical properties were also studied and used to produce functional 3D LED.

EPFL2017

Increasing Functionality of III-V Nanowires on Silicon Substrates

Wonjong Kim

Progress in nanotechnology, including fabrication and characterization tools, opened up the unprecedented low dimensional materials era, where we can manipulate and structure matter on a size scale that we could not reach before. Due to many interesting properties of nano-sized materials different from their bulk counterparts, we now have opportunities both in combining new material properties with existing technologies and in establishing new technologies. In this context, combining mature silicon technology with III-V compound semiconductors in order to utilise the advantages of both materials has been the main goal of this thesis. In hetero-epitaxial systems, there are difficulties associated with the lattice mismatch, polarity difference, and thermal expansion coefficient difference of the two materials that can lead to dislocations, anti-phase boundaries, strain, and even cracking. Among many other candidates in low dimensional materials system, one-dimensional nanowire is one of the most extensively investigated architectures to overcome most of these challenges thanks to the inherent small dimensions of interfaces and interesting electronic & photonic properties. Despite previous efforts in integrating GaAs nanowires with silicon in a position-controlled manner using a patterned dielectric mask, the fundamental understanding of nanowire growth mechanisms in the small openings was still missing. The core part of this work is dedicated to providing a clear pathway for realistic integration of III-Vs on silicon in the form of ordered nanowire arrays. I demonstrated that there is a critical aspect ratio of the pattern holes(diameter/height) which guarantees a high yield of vertical nanowires once we have well positioned Ga droplets prior to nanowire growth. We pointed out the importance of the initial GaAs crystal at the bottom of the pattern holes. A uniformly distributed initial nucleation along the oxide mask and silicon substrate line interface allows for vertical growth of nanowire and this understanding results in reproducible and high vertical yield (95%) of GaAs nanowire arrays on silicon. Having obtained reproducible growth of GaAs nanowire arrays, morphological properties of nanowires were investigated. A time series growth study revealed the length and diameter evolution in regular array systems. We found that increasing As4 flux can effectively narrow down the length distributions without degrading nanowire vertical yield. In addition, we could obtain ultrathin GaAs nanowire having diameters of 20 nm or even less in ordered array systems by taking advantage of the self-catalyzed growth method. Finally, electrical properties of silicon/GaAs nanowire heterojunctions were investigated with the goal of increasing their functionalities. Our preliminary study highlighted that we could effectively engineer Si/GaAs nanowire heterojunctions by in situ doping during the nanowire growth in the molecular beam epitaxy system.

EPFL2020