Growth of nanowire arrays from micron-feature templates
Graph Chatbot
Chat with Graph Search
Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.
DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.
We show a scalable process to fabricate reusable silicon templates with funnel- and cone-shaped traps for the capillary-assisted particle assembly (CAPA) technique. The assembly yield of 100 nm AuNPs in funnel traps is as high as 94% and the median of the ...
This work presents a systematic analysis of the transport mechanism and surface passivation of tunneling oxide (SiO2)/p-type poly-silicon (poly-Si(p)) junctions applied to p-type crystalline silicon (c-Si) solar cells by means of TCAD numerical simulations ...
This thesis is dedicated to the growth and characterization of the optoelectronic properties of III-V semiconductor nanostructures namely nanowires and nanoscale membranes. III-V semiconductors possess promising intrinsic properties like direct band gap, h ...
Progress in nanotechnology, including fabrication and characterization tools, opened up the unprecedented low dimensional materials era, where we can manipulate and structure matter on a size scale that we could not reach before. Due to many interesting pr ...
Background: Elongated nanostructures, such as nanowires, have attracted significant attention for application in silicon-based solar cells. The high aspect ratio and characteristic radial junction configuration can lead to higher device performance, by inc ...
Silicon is today the main material used in electronics. It is a very advanced and mature technology. It is therefore clear that new technological concepts and materials should be introduced through the integration on the silicon platform. III-V semiconduct ...
Multi-scale integration remains the primary challenge in the fabrication of miniature piezoresistive sensors, as the co-fabrication of a silicon nanowire along with a microscale shuttle is the main architecture facilitating high-sensitivity transduction. T ...
Institute of Electrical and Electronics Engineers2017
We demonstrate high-performance GaN power metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on silicon substrate based on a nanowire tri-gate architecture. The common issue of partial removal of carriers by nanowire etching in GaN tri ...
The goal of this thesis is to master the synthesis of GaAs nanowires ensembles on Si for their application in solar cells. Semiconductor nanowires present promising characteristics for photovoltaic applications: they benefit from their longitudinal high as ...
Monolayer doping (MLD) of silicon substrates at the nanoscale is a powerful method to provide controlled doses of dopants and defect-free materials. However, this approach requires the deposition of a thick SiO2 cap layer to limit dopant evaporation during ...
