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Reconfigurable Logic Gates Based on Programable Multistable Mechanisms

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Reducing the number of AND gates plays a central role in many cryptography and security applications. We propose a logic synthesis algorithm and tool to minimize the number of AND gates in a logic network composed of AND, XOR, and inverter gates. Our appro ...

ASSOC COMPUTING MACHINERY2019

Triboelectric‐TFT Flip‐Flop for Bistable Latching of Dielectric Elastomer Actuators

Danick Briand, Herbert Shea, Rubaiyet Iftekharul Haque, Alexis Pierre Henri Marette, Xiaobin Ji, Ronan Julien Hinchet

A high‐voltage flip‐flop combining two self‐powered soft sensors with a flexible high‐voltage thin film transistor (HVTFT) is reported, and is used to electrically latch dielectric elastomer actuators (DEAs) in zero and high‐strain states. Two touch‐actuat ...

2019

More Results on Shortest Linear Programs

Subhadeep Banik

At the FSE conference of ToSC 2018, Kranz et al. presented their results on shortest linear programs for the linear layers of several well known block ciphers in literature. Shortest linear programs are essentially the minimum number of 2-input xor gates r ...

2019

Photoactivatable dyes enable single-mol. imaging in biol. Despite progress in the development of new fluorophores and labeling strategies, many cellular compartments remain difficult to image beyond the limit of diffraction in living cells. For example, li ...

2019

A Magnet-Based Timing System to Detect Gate Crossings in Alpine Ski Racing

Kamiar Aminian, Benedikt Fasel

In alpine skiing, intermediate times are usually measured with photocells. However, for practical reasons, the number of intermediate cells is limited to three⁻four, making a detailed timing analysis difficult. In this paper, we propose and validate a magn ...

2019

Steady state in experimentally produced turbidity current under a large amount of suspension supply

Giovanni De Cesare, Shun Nomura, Jumpei Hitomi

Turbidity current is generated in an inclined lock-gate flume under a large amount of suspension supply. By opening the gate, turbidity current generates and flows to downstream. The turbidity current maintains its interface structure and progresses with c ...

2019

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Developing large arrays of single-photon avalanche diodes (SPADs) with on-chip time-correlated single-photon counting (TCSPC) capabilities continues to be a difficult task due to stringent silicon real estate constraints, high data rates and system complex ...

2019

Improvements to Boolean resynthesis

Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù

In electronic design automation Boolean resynthesis techniques are increasingly used to improve the quality of results where algebraic methods hit local minima Boolean methods rely on complete functional properties of a logic circuit, preferably including ...

IEEE2018

Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers

Cunxi Yu, Maciej Jerzy Ciesielski

The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2(m)) using GF(2) models of its logi ...

IEEE2018

Small-animal and endoscopic PET detector modules based on multichannel digital silicon photomultipliers

Edoardo Charbon, Augusto Carimatto, Esteban Venialgo Araujo

In time-of-flight (TOF) positron emission tomography (PET), the coincidence resolving time (CRT) has a strong influence on the overall performance. Multichannel digital silicon photomultipliers (MD-SiPMs) are able to obtain several timestamps for gamma pho ...

2017