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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

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Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

Surface potential compact model for embedded flash devices oriented to IC memory design

Impact of body biasing on the retention time of gain-cell memories

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Numerical and Compact Modeling of Embedded Flash Memory Devices Targeted for IC Design

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Surface potential compact model for embedded flash devices oriented to IC memory design

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Numerical and Compact Modeling of Embedded Flash Memory Devices Targeted for IC Design

Impact of body biasing on the retention time of gain-cell memories

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Surface potential compact model for embedded flash devices oriented to IC memory design

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Surface potential compact model for embedded flash devices oriented to IC memory design