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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

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Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

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Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

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Surface potential compact model for embedded flash devices oriented to IC memory design

Impact of body biasing on the retention time of gain-cell memories

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Numerical and Compact Modeling of Embedded Flash Memory Devices Targeted for IC Design

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Surface potential compact model for embedded flash devices oriented to IC memory design

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Surface potential compact model for embedded flash devices oriented to IC memory design

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Numerical and Compact Modeling of Embedded Flash Memory Devices Targeted for IC Design

Impact of body biasing on the retention time of gain-cell memories

Using Managed Runtime Systems to Tolerate Holes in Wearable Memories

A Distributed Interleaving Scheme for Efficient Access to WideIO DRAM Memory

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

Surface potential compact model for embedded flash devices oriented to IC memory design