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P-GaN Tri-Gate MOS Structure for Normally-Off GaN Power Transistors

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A Common Core Model for Junctionless Nanowires and Symmetric Double Gate FETs

Jean-Michel Sallese, Farzan Jazaeri, Lucian Barbut, Christophe Lallement

In this brief, we evidence the link between planar and cylindrical junctionless FETs from the electrostatics point of view. In particular, we show that an approximate solution of the Poisson-Boltzmann equation for junctionless nanowires can be mapped on th ...

Institute of Electrical and Electronics Engineers2013

Beyond Scaling

Luca De Michielis

Over the recent decades, the balance between increasing the complexity of computer chips and simultaneously reducing cost per bit has been accommodated by down-scaling. While extremely successful in the past, this approach now faces grave limitations leadi ...

EPFL2012

Multi-gate Si nanowire MOSFETs

Mohammad Najmzadeh

Multi-gate devices e.g. gate-all-around (GAA) Si nanowires and FinFETs are promising can- didates for aggressive CMOS downscaling. Optimum subthreshold slope, immunity against short channel effect and optimized power consumption are the major benefits of s ...

EPFL2012

Tri-Gate Normally-Off GaN Power MISFET

Elison de Nazareth Matioli, Bin Lu

We present a new normally-off GaN transistor-the tri-gate normally-off GaN metal-insulator-semiconductor field-effect transistor (MISFET). Due to the excellent channel control of a new 3-D gate structure, a breakdown voltage of 565 V has been achieved at a ...

Ieee-Inst Electrical Electronics Engineers Inc2012

Low Leakage Normally-off Tri-gate GaN MISFET

Elison de Nazareth Matioli, Bin Lu

A new tri-gate normally-off GaN metal-insulator-semiconductor field effect transistor (MISFET) is presented in this paper. By using a three-dimensional gate structure with combination of a sub-micron gate recess, the new device achieves a very low off-stat ...

Ieee2012

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

Institute of Electrical and Electronics Engineers2012

Coulomb blockade phenomenon in ultra-thin gold nanowires

Hoël Maxime Guérin

Ultra-thin gold nanowires with uniform diameters of 2 nm and lengths of over 100 μm are synthesized via the reduction of gold(III) chloride in an oleylamine matrix. The gold nanowires, dispersed on an oxidized substrate, are top-contacted with metallic ele ...

American Institute of Physics2012

Coulomb blockade in a granular material made of gold nanowires

Hoël Maxime Guérin

Uniform, 2 nm diameter gold nanowires were synthesized through the reduction of gold(III) chloride in an oleylamine matrix. They were top-contacted on a Si/SiO2 substrate with metallic electrodes to manufacture back-gated transistors. Due to thermal breaka ...

2012

InAlN/GaN HEMTs for Operation in the 1000 degrees C Regime: A First Experiment

Nicolas Grandjean, Jean-François Carlin

GaN-based heterostructures, and here, particularly, the lattice matched InAlN/GaN configuration, possess high chemical and thermal stability. Concentrating on refractory metal contact schemes, HEMT devices have been fabricated allowing high-temperature 1-M ...

2012

Field-Effect Transistors Based on ZnO Nanowires

Daniel Dominik Kälblein

Semiconductor nanowires are an emerging class of materials with great potential for applications in future electronic devices. The small footprint and the large charge-carrier mobilities of nanowires make them potentially useful for applications with high- ...

EPFL2011