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Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

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Memory chip or memory array for wide-voltage range in-memory computing using bitline technology

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Multilevel-cell phase-change memory

Differential vector storage for dynamic random access memory

Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications

A Fully-Digital Spectrum Shaping Signaling for Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces

Sort vs. Hash Join Revisited for Near-Memory Execution

Sort vs. Hash Join Revisited for Near-Memory Execution

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

BuMP: Bulk Memory Access Prediction and Streaming

Design of Digital SoC for Operation at High Temperatures

Differential vector storage for dynamic random access memory

Multilevel-cell phase-change memory

BuMP: Bulk Memory Access Prediction and Streaming

Design of Digital SoC for Operation at High Temperatures

Sort vs. Hash Join Revisited for Near-Memory Execution

Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware

A Fully-Digital Spectrum Shaping Signaling for Serial-Data Transceiver with Crosstalk and ISI Reduction Property in Multi-Drop Memory Interfaces

Sort vs. Hash Join Revisited for Near-Memory Execution

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology