Publication

Phase–frequency detecting time-to-digital converter

Related publications (33)

About
Privacy
Disclaimer

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Phase–frequency detecting time-to-digital converter

Graph Chatbot

Chat with Graph Search

Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

High-Performance CMOS SPAD-Based Sensors for Time-of-Flight PET Applications

Development of a Data Concentrator ASIC for the High Luminosity upgrade of the CMS Outer Tracker detector with tracking trigger

Low Noise Clock Generation: Modeling, Analysis and Implementation

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Understanding the diversity of the metal-organic framework ecosystem

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

An All-Digital 1 Mbps, 57 pJ/bit Bluetooth Low Energy (BLE) Backscatter ASIC in 65 nm CMOS

High-Performance CMOS SPAD-Based Sensors for Time-of-Flight PET Applications

Low Noise Clock Generation: Modeling, Analysis and Implementation

Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID

Development of a Data Concentrator ASIC for the High Luminosity upgrade of the CMS Outer Tracker detector with tracking trigger

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Understanding the diversity of the metal-organic framework ecosystem

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization