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A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control

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A 67-fsrms Jitter, −130 dBc/Hz In-Band Phase Noise, −256-dB FoM Reference Oversampling Digital PLL With Proportional Path Timing Control

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A Cryo-CMOS Wideband Quadrature Receiver With Frequency Synthesizer for Scalable Multiplexed Readout of Silicon Spin Qubits

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

Low-Power and Wide-Tuning Range Frequency Generation for FMCW Radars in Advanced CMOS Technologies

A Low-Jitter and Low-Spur Charge-Sampling PLL

A 60 GHz QDCO with 11 GHz Seamless Tuning for Low-Power FMCW Radars in 22-nm FDSOI

Low Noise Clock Generation: Modeling, Analysis and Implementation

Evidence of Smaller 1/F Noise in AlScN-Based Oscillators Compared to AlN-Based Oscillators

A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Discrete Time Analysis of Phase Detector Linear Range Extension in Sub-Sampling PLL

Resistive Coupled VO2 Oscillators for Image Recognition