Publications associées à Logic family

Inversion optimization in majority-inverter graphs

Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Eleonora Testa, Odysseas Zografos

Many emerging nanotechnologies realize majority gates as primitive building blocks and they benefit from a majority-based synthesis. Recently, Majority-Inverter Graphs (MIGs) have been introduced to abstract these new technologies. We present optimi ...

Ieee2016

Highly Scalable Digital Silicon Photonic MEMS Switches

Niels Quack

Optical circuit switches with fast switching times can provide rapidly reconfigurable bandwidth in data center networks. Silicon photonic switches are attractive candidates with their fast response times and CMOS process compatibility. In this paper, we re ...

Ieee-Inst Electrical Electronics Engineers Inc2016

Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This work reports on a heterogeneous integration of resistive memories into the Back-End-of-the-Line of 180nm standard CMOS foundry chips. A TaOx-based ReRAM technology with materials and processes fully CMOS compatible has been developed and characterized ...

Elsevier2015

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Xifan Tang, Gain Kim

Nowadays, Field Programmable Gate Arrays (FPGA) exploit Look-Up Tables (LUTs) to generate logic functions. A K-input LUT can implement any Boolean functions with K inputs. Thanks to this flexibility, LUTs remained concep ...

2015

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Hassan Ghasemzadeh Mohammadi

Controllable polarity silicon nanowire transistors are among the promising candidates to replace current CMOS in the near future owing to their superior electrostatic characteristics and advanced functionalities. From a circuit testing point of view, it is ...

IEEE2015

Full Swing 20 GHz Frequency Divider with 1 V Supply Voltage in FD-SOI 28 nm Technology

Yusuf Leblebici, Tugba Demirci, Duygu Kostak, Hasene Gülperi Özsema

In this paper we present the design of a pro- grammable frequency divider in 28 nm FD-SOI CMOS technology. It consists of the cascade of a divide-by-2 cell and divide- by-2/3 blocks. The final circuit is capable of dividing by even numbers between 128 and ...

2015

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti

Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequ ...

2015

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This paper presents an extended model for transient and ac circuit-level simulation of minority carriers propagation through the substrate of smart power integrated circuits (ICs). A p-n junction and a diffusion resistor with capacitive components are prop ...

Institute of Electrical and Electronics Engineers2015

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Logic family

Inversion optimization in majority-inverter graphs

Highly Scalable Digital Silicon Photonic MEMS Switches

Polarity Control at Runtime

Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

An Implantable High-Voltage Cortical Stimulator for Post-stroke Rehabilitation Enhancement with High-Current Driving Capacity

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

Full Swing 20 GHz Frequency Divider with 1 V Supply Voltage in FD-SOI 28 nm Technology

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs

Graph Chatbot

Chattez avec Graph Search

Highly Scalable Digital Silicon Photonic MEMS Switches

Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process

Inversion optimization in majority-inverter graphs

Polarity Control at Runtime

Towards More Efficient Logic Blocks by Exploiting Biconditional Expansion

An Implantable High-Voltage Cortical Stimulator for Post-stroke Rehabilitation Enhancement with High-Current Driving Capacity

Full Swing 20 GHz Frequency Divider with 1 V Supply Voltage in FD-SOI 28 nm Technology

Fault Modeling in Controllable Polarity Silicon Nanowire Circuits

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

Modeling Minority Carriers Related Capacitive Effects for Transient Substrate Currents in Smart Power ICs