Frequency synthesizer | EPFL Graph Search

A frequency synthesizer is an electronic circuit that generates a range of frequencies from a single reference frequency. Frequency synthesizers are used in many modern devices such as radio receivers, televisions, mobile telephones, radiotelephones, walkie-talkies, CB radios, cable television converter boxes, satellite receivers, and GPS systems. A frequency synthesizer may use the techniques of frequency multiplication, frequency division, direct digital synthesis, frequency mixing, and phase-locked loops to generate its frequencies. The stability and accuracy of the frequency synthesizer's output are related to the stability and accuracy of its reference frequency input. Consequently, synthesizers use stable and accurate reference frequencies, such as those provided by a crystal oscillator. Types Three types of synthesizer can be distinguished. The first and second type are routinely found as stand-alone architecture: direct analog synthesis (also called a mix-filter-divi

Ultra-low noise microwave signal generation with an optical frequency comb

Christophe Alexandre

Photonic synthesis of radio frequency waveforms revived the quest for unrivalled microwave purity by its seducing ability to convey the benefits of the optics to the microwave world. In this contribution, we will present a high-fidelity transfer of frequency stability between an optical reference and a microwave signal via a low-noise fiber-based frequency comb and cutting-edge photo-detection techniques. We will show the generation of the purest microwave signal with a fractional frequency stability below 6.5 x 10(-16) at 1 s and a timing noise floor below 41 zs Hz(-1/2) (phase noise below-173 dBc Hz(-1) for a 12 GHz carrier). This outclasses existing sources and promises a new era for state-of-the-art microwave generation. The characterization is achieved through a heterodyne cross-correlation scheme with lowermost detection noise. This unprecedented level of purity can impact domains such as radar systems, telecommunications and time-frequency metrology. The measurements methods developed here can benefit the characterization of a broad range of signals.

SPIE-INT SOC OPTICAL ENGINEERING2018

A low-power 2.4 GHz CMOS receiver using BAW resonators

Jérémie Chabloz

It has already been a few years since the first appearance of micro-electromechanical systems (MEMS) in academic research. Since then, a broad number of devices have been designed under this generic term. Bulk-acoustic wave (BAW) resonators are among the few of them which have become exploited at industrial level. They are mainly used to implement filters for mainstream telecommunication applications. In a different domain, potential applications for integrated wireless transceivers are flourishing. While some of them require always higher data rates, others need devices with low data rate but even lower power consumption. The goal of this thesis is to explore ways of using BAW resonators to implement building blocks for such a low-power radio and actually verify the postulate that this could help improving power consumption as well as miniaturize key functionalities. For the active integrated circuit part, the choice of a standard digital 0.18µm CMOS process established itself for its low cost and ubiquity. The specifications for the developed radio receiver are calculated for a physical layer derived from the well known Bluetooth communication protocol in the 2.4GHz ISM band with similar applications scenarii but with much lower data rates and wider channel spacing. After presenting the advantages and limitations of the devices, the implications for using BAWresonators to implement a low-power radio are investigated at circuit and system levels and a super-heterodyne architecture is proposed. A selective low-noise amplifier (LNA) is used at the circuit front-end to yield image and blocker rejection. Measurements for the RF front-end comprising an external balun, the selective LNA, a first downconversionmixer and an intermediate-frequency (IF) amplifier showed an overall noise figure of 11dB for a current consumption of 1.5mA under 1.2V. The high selectivity of the design yields an image rejection ratio of at least 50dB and allows to decrease linearity requirements and thus power consumption. A slightly improved version of the same front-end integrated together with the analog baseband signal processing chain but still using external local oscillators showed sensitivities of -96dBm at 100kbps symbol rate and -93dBm at 200kbps with an external state-of-the art FSK demodulator, allowing to extrapolate a global noise figure of 12.2dB for a global current consumption of 2.3mA under 1.2V. The proposed solution for the frequency synthesis uses both a BAW oscillator for the first downconversion to IF and a quadrature quasi-harmonic relaxation oscillator to translate the signals to baseband. The relaxation oscillator is embedded within a phase-locked loop (PLL) for which all the required blocks are discussed. Particularly, a novel modular multi-modulus frequency divider is presented, which does not necessitate complicated logic to yield the wanted division ratio and uses dynamic logic. The necessary digital circuitry to control the frequency generation is discussed as well. Finally, measurements for the complete receiver using the proposed frequency synthesis as well as digital control and demodulator implemented on FPGA are presented.

EPFL2008

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009