Frequency divider | EPFL Graph Search

A frequency divider, also called a clock divider or scaler or prescaler, is a circuit that takes an input signal of a frequency, f_{in}, and generates an output signal of a frequency: : f_{out} = \frac{f_{in}}{n} where n is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications. Analog Analog frequency dividers are less common and used only at very high frequencies. Digital dividers implemented in modern IC technologies can work up to tens of GHz. Regenerative A regenerative frequency divider, also known as a Miller frequency divider, mixes the input signal with the feedback signal from the mixer. The feedback signal is f_{in}/2. This produces sum and difference frequencies f_{in}/2, 3f_{in}/2 at the outpu

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

A novel frequency synthesizer with a strong emphasis on low-power consumption (2mW) was developed for this thesis. A BAW-resonator was used for the design of the high-frequency oscillator. The BAW's high Q-Factor ensured a minimal power consumption, while providing outstanding phase noise performance. This type of frequency synthesizer can be implemented in practically every mobile wireless system standard, which is relying on batteries as the power supply, such as Bluetooth, Zigbee and others. For this work, a Bluetooth-compatible standard was taken in order to derive the system specifications. The frequency synthesizer then was designed and implemented in a 180nm CMOS process. The approach of the "Sliding-IF" architecture was chosen and modified in order to take full advantage on the BAW oscillator. Therefore a two-stage frequency translation of the signal was necessary, similar to the super-heterodyne transceiver topology. The channel selection and the frequency error correction is done at the second stage, since the BAW-based oscillator does practically not provide any frequency tuning. For this, a Delta-Sigma-Modulator based Fractional-N PLL was developed. A system supply voltage of 1.2V was chosen in order to keep power consumption as low as possible. This supply voltage can also be easily supplied by AA or AAA-batteries and a low-voltage regulator. The most important technique to reduce overall power consumption was to reduce the high-frequency requirements to the system blocks. This was done by modifying the "Sliding-IF" architecture and by the use of the BAW resonator. The minimization of the power consumption required careful choice and design of each of the system blocks. For this, several approaches were analyzed, especially the topology of each block and its optimization were important. A special emphasis on the analysis, design and discussion was also made on the noise, and especially the phase noise. A ring oscillator, a LC-VCO and a BAW-oscillator were implemented and measured in order to validate the theory and the simulation results. The complete frequency synthesizer with an Automatic Amplitude Control, Frequency Dividers, Mixer, Charge-Pump, Phase-Frequency Detector and a Delta-Sigma-Modulator was designed and implemented. This thesis was elaborated in the frame of the MiNAMI and MiMOSA projects of the European research programme (FP6).

EPFL2009

Driven dual phase lock loop

Pierre-André Farine, Steve Tanner, Yazhou Zhao

The invention relates to a phase lock loop (100) comprising: - a loop filter (140), - a voltage controlled oscillator (150), - a frequency divider (160), - a frequency lock detector (113), able to emit a frequency lock indication signal (LOCK), - a digital phase and frequency comparator (110), - a charge pump (111), and - an analogue phase comparator (120). The loop is essentially characterized in that it further comprises a switch (130) equipped with an output connected to the loop filter (140), and with two inputs, this switch being able to selectively connect the first input, originating from the analogue phase comparator, to its output in response to the lock indication signal; and its second input, originating from the digital phase and frequency comparator, to its output, in the absence of the lock indication signal.

2016

Low power frequency synthesizer for mobile communications systems

Imre Kovacs

EPFL2009