Publications associées à Histoire des ordinateurs personnels

DyNCA: Real-time Dynamic Texture Synthesis Using Neural Cellular Automata

Sabine Süsstrunk, Ehsan Pajouheshgar, Yitao Xu, Tong Zhang

Current Dynamic Texture Synthesis (DyTS) models can synthesize realistic videos. However, they require a slow iterative optimization process to synthesize a single fixed-size short video, and they do not offer any post-training control over the synthesis p ...

Ieee Computer Soc2023

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Paolo Ienne, Mikhail Asiatici

Efficient large-scale graph processing is crucial to many disciplines. Yet, while graph algorithms naturally expose massive parallelism opportunities, their performance is limited by the memory system because of irregular memory accesses. State-of-the-art ...

IEEE COMPUTER SOC2021

The open EEGLAB portal Interface: High-Performance computing with EEGLAB

Fiorenzo Artoni

EEGLAB signal processing environment is currently the leading open-source software for processing electroencephalographic (EEG) data. The Neuroscience Gateway (NSG, nsgportal.org) is a web and API-based portal allowing users to easily run a variety of neur ...

2021

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of DRAMs, gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power and CMOS-compatible alternative to conventional SRAM. GC-eDRAM achieves high memory density as it relies on a storage cell that can be implemented with as few as ...

IEEE2020

Interactions between Personality, Depression, Anxiety and Cognition to Understand Early Stage of Alzheimer's Disease

Valérie Rita Madeleine Zufferey

The multifaceted nature of Alzheimer's disease (AD) and Mild cognitive impairment (MCI) can lead to wide inter-individual differences in disease manifestation in terms of brain pathology and cognition. The lack of understanding of phenotypic diversity in A ...

BENTHAM SCIENCE PUBL LTD2020

Blade: An in-Cache Computing Architecture for Edge Devices

David Atienza Alonso, Marina Zapater Sancho, Alexandre Sébastien Julien Levisse, Marco Antonio Rios, William Andrew Simon, Yasir Mahmood Qureshi

Area and power constrained edge devices are increasingly utilized to perform compute intensive workloads, necessitating increasingly area and power efficient accelerators. In this context, in-SRAM computing performs hundreds of parallel operations on spati ...

2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Modeling of Total Ionizing Dose Degradation on 180-nm n-MOSFETs Using BSIM3

Nergiz Sahin Solmaz, Mustafa Berke Yelten, Sadik Ilik

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal-oxide-semiconductor field-effect transist ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Hardware-conscious Hash-Joins on GPUs

Anastasia Ailamaki, Manolis Karpathiotakis, Raja Appuswamy, Periklis Chrysogelos, Panagiotis Sioulas

Traditionally, analytical database engines have used task parallelism provided by modern multisocket multicore CPUs for scaling query execution. Over the past few years, GPUs have started gaining traction as accelerators for processing analytical queries d ...

IEEE2019

Sub-Thermionic Scalable III-V Tunnel Field-Effect Transistors Integrated on Si (100)

Mihai Adrian Ionescu, Kirsten Emilie Moselund

We present scalable III-V heterojunction tunnel FETs fabricated using a Si CMOS-compatible FinFET process flow and integrated on Si (100) substrates. The tunneling junction is fabricated through self-aligned selective p(+) GaAsSb raised source epitaxial re ...

IEEE2019