Publications associées à Circuit asynchrone

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Mohammad Khaja Nazeeruddin, Olga Syzgantseva

The engineering of tin halide perovskites has led to the development of p-type transistors with field-effect mobilities of over 70 cm2 V-1 s-1. However, due to their background hole doping, these perovskites are not suitable for n-type transistors. Ambipol ...

Nature Portfolio2024

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Andreas Peter Burg, Alexios Konstantinos Balatsoukas Stimming, Andreas Toftegaard Kristensen, Yifei Shen, Yuqing Ren, Chuan Zhang

Compared with the bit-wise successive cancellation list (SCL) decoding of polar codes, the node-based Fast SCL decoding significantly reduces the decoding latency by identifying special constituent codes and decoding these in parallel. To further reduce th ...

IEEE2022

Improving First-Order Threshold Implementations of SKINNY

Andrea Felice Caforio, Daniel Patrick Collins, Subhadeep Banik, Ognjen Glamocanin

Threshold Implementations have become a popular generic technique to construct circuits resilient against power analysis attacks.In this paper, we look to devise efficient threshold circuits for the lightweight block cipher family SKINNY. The only threshol ...

Springer, Cham2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Giovanni De Micheli, Eleonora Testa, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scalin ...

Association for Computing Machinery2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Giovanni De Micheli, Heinz Riener, Shubham Rai, Akash Kumar

Emerging reconfigurable nanotechnologies allow the implementation of self-dual functions with a fewer number of transistors as compared to traditional CMOS technologies. To achieve better area results for Reconfigurable Field-Effect Transistors (RFET)-base ...

2021

Que Sera Consensus: Simple Asynchronous Agreement with Private Coins and Threshold Logical Clocks

Bryan Alexander Ford, Philipp Svetolik Jovanovic

It is commonly held that asynchronous consensus is much more complex, difficult, and costly than partially-synchronous algorithms, especially without using common coins. This paper challenges that conventional wisdom with que sera consensus QSC, an approac ...

2020

Digital Design with Implicit State Machines

Martin Odersky, Aleksandar Prokopec, Fengyun Liu

Claude Shannon, in his famous thesis (1938), revolutionized circuit design by showing that Boolean algebra subsumes all ad-hoc methods that are used in designing switching circuits, or combinational circuits as they are commonly known today. But what is ...

2020

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Yusuf Leblebici, Firat Çelik, Ayça Akkaya

This paper presents a 9-bit 222 MS/s low-power asynchronous single-bit/cycle successive approximation register (SAR) ADC. The SAR ADC combines techniques such as asynchronous clocking, binary-weighted custom-designed capacitive DAC with small unit capacito ...

IEEE2020

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Circuit asynchrone

Strain relaxation and multidentate anchoring in n-type perovskite transistors and logic circuits

Electronic transport in graphene nanoribbon junctions

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Improving First-Order Threshold Implementations of SKINNY

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection

Que Sera Consensus: Simple Asynchronous Agreement with Private Coins and Threshold Logical Clocks

Digital Design with Implicit State Machines

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Graph Chatbot

Chattez avec Graph Search

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies

Que Sera Consensus: Simple Asynchronous Agreement with Private Coins and Threshold Logical Clocks

A Low-Power 9-Bit 222 MS/s Asynchronous SAR ADC in 65 nm CMOS

Digital Design with Implicit State Machines

Improving First-Order Threshold Implementations of SKINNY

A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection