Concept

Clock skew

Publications associées (39)

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Paolo Ienne, Lana Josipovic

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Low Noise Clock Generation: Modeling, Analysis and Implementation

Duygu Kostak

The aim of this thesis is to implement, analyze and improve the selected low noise clock generation and distribution techniques for ADC implementations. The thesis is divided into two parts. The first part focuses on the sampling phase generation and distr ...

EPFL2021

A 510-pW 32-kHz Crystal Oscillator With High Energy-to-Noise-Ratio Pulse Injection

Kyojin Choo, Li Xu

This article introduces a 32-kHz crystal oscillator (XO) with high energy-to-noise-ratio pulse injection at subharmonic frequency. A T/4-delay clock slicer is proposed to convert the sinusoidal crystal waveform into an output clock of 32 kHz and to introdu ...

IEEE2021

Combining Dynamic & Static Scheduling in High-level Synthesis

Paolo Ienne, Lana Josipovic

ASSOC COMPUTING MACHINERY2020

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Andrea Bonetti

As an increase of intelligent and self-powered devices is forecasted for our future everyday life, the implementation of energy-autonomous devices that can wirelessly communicate data from sensors is crucial. Even though techniques such as voltage scaling ...

EPFL2019

Inverse Gating for Low Energy Encryption

Subhadeep Banik

In this paper we explore the technique of "inverse gating" which is a significant improvement over the "round gating" technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit elemen ...

2018

Inverse Gating for Low Energy Block Ciphers

Francesco Regazzoni, Subhadeep Banik

In this paper we explore the technique of “inverse gating” which is a significant improvement over the ”round gating” technique introduced in HOST 2016. Round gating worked by generating timing signals to separate glitch propagation from one circuit elemen ...

2018

The design of Wren, a Fast and Scalable Transactional Causally Consistent Geo-Replicated Key-Value Store

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

This paper presents the design of Wren, a new geo-replicated key-value store that achieves Transactional Causal Consistency. Wren leverages two design choices to achieve higher performance and better scalability than existing systems. First, Wren uses hybr ...

2017

Okapi : Causally Consistent Geo-Replication Made Faster, Cheaper and More Available

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

Okapi is a new causally consistent geo-replicated key-value store. Okapi leverages two key design choices to achieve high performance. First, it relies on hybrid logical/physical clocks to achieve low latency even in the presence of clock skew. Second, Oka ...

2017

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