Publications associées à Architecture de mémoire à multiples canaux

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi

The increasing complexity of transformer models in artificial intelligence expands their computational costs, memory usage, and energy consumption. Hardware acceleration tackles the ensuing challenges by designing processors and accelerators tailored for t ...

2024

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Gyrokinetic simulations on many- and multi-core architectures with the global electromagnetic Particle-In-Cell Code ORB5

Laurent Villard, Stephan Brunner, Emmanuel Lanti, Noé Thomas Elie Ohana, Claudio Gheller

Gyrokinetic codes in plasma physics need outstanding computational resources to solve increasingly complex problems, requiring the effective exploitation of cutting-edge HPC architectures. This paper focuses on the enabling of ORB5, a state-of-the-art, fir ...

2020

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

David Atienza Alonso, Amir Aminifar, Miguel Peon Quiros, Adriana Arza Valdes, Elisabetta De Giovanni

In the recent Internet-of-Things (IoT) era where biomedical applications require continuous monitoring of relevant data, edge computing keeps gaining more and more importance. These new architectures for edge computing include multi-core and parallel compu ...

2020

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

David Atienza Alonso, Marina Zapater Sancho, Luis Maria Costero Valero, Arman Iranfar

The advent of online video streaming services along with the users' demand for high-quality contents require High Efficiency Video Coding (HEVC), which provides higher quality and compression at the cost of increased complexity. On one hand, HEVC exposes a ...

2020

A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

Edoardo Charbon, Ivan Michel Antolovic, Chunmin Zhang, Scott Anthony Lindner, Juan Mata Pavia, Martin Wolf

A 252 x 144 single-photon avalanche diode (SPAD) pixel sensor, called Ocelot, is reported for light detection and ranging (LiDAR). The sensor, fabricated in the 180-nm CMOS technology, features 1728 12-bit time-to-digital converters (TDCs) with 48.8-ps res ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Milkomeda: Safeguarding the Mobile GPU Interface Using WebGL Security Checks

Mathias Josef Payer

GPU-accelerated graphics is commonly used in mobile applications. Unfortunately, the graphics interface exposes a large amount of potentially vulnerable kernel code (i.e., the GPU device driver) to untrusted applications. This broad attack surface has resu ...

ASSOC COMPUTING MACHINERY2018

Fat Caches For Scale-Out Servers

Babak Falsafi, Boris Robert Grot, Stavros Volos

The authors propose a high-capacity cache architecture that leverages emerging high-bandwidth memory modules. High-capacity caches capture the secondary data working sets of scale-out workloads while uncovering significant spatiotemporal locality across da ...

Institute of Electrical and Electronics Engineers2017

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Architecture de mémoire à multiples canaux

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Miniaturised, Wireless and Distributed Neural Interface Toward Cortical Visual Prosthesis

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Sampling-Based AQP in Modern Analytical Engines

Gyrokinetic simulations on many- and multi-core architectures with the global electromagnetic Particle-In-Cell Code ORB5

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

Milkomeda: Safeguarding the Mobile GPU Interface Using WebGL Security Checks

Fat Caches For Scale-Out Servers

Graph Chatbot

Chattez avec Graph Search

Miniaturised, Wireless and Distributed Neural Interface Toward Cortical Visual Prosthesis

Accelerator-driven Data Arrangement to Minimize Transformers Run-time on Multi-core Architectures

Milkomeda: Safeguarding the Mobile GPU Interface Using WebGL Security Checks

A 30-frames/s, 252 x 144 SPAD Flash LiDAR With 1728 Dual-Clock 48.8-ps TDCs, and Pixel-Wise Integrated Histogramming

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Real-Time Personalized Atrial Fibrillation Prediction on Multi-Core Wearable Sensors

Resource Management for Power-Constrained HEVC Transcoding Using Reinforcement Learning

Fat Caches For Scale-Out Servers

Sampling-Based AQP in Modern Analytical Engines

Gyrokinetic simulations on many- and multi-core architectures with the global electromagnetic Particle-In-Cell Code ORB5