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Publications associées (18)

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A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Giovanni De Micheli, Eleonora Testa, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scalin ...

Association for Computing Machinery2021

Pushing the Limits of Efficiency and Power Density in High-Frequency Power Conversion Based on Wide-Band-Gap Technologies

Armin Jafari

The emergence of wide-band-gap (WBG) power transistors with low conduction losses and high-speed switching speeds has paved the way for more-than-ever efficient power electronics systems and huge energy saving potentials. Likewise, power density- the ratio ...

EPFL2021

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

Time-of-flight device and 3d optical detector

Christian Enz, Assim Boukhayma, Antonino Caizzone

A Time-of-flight optical device and a 3D optical detector comprising a CMOS integrated circuit with an array of photosensitive pixels that are, at least in part, interconnected to form macro-pixels (180). Each macro-pixel (180) groups a plurality of indivi ...

2020

Impact of Fin Width on Tri-Gate GaN MOSHEMTs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Giovanni Santoruvo, Taifang Wang

In this paper, we present a detailed investigation of the impact of fin width (w(fin)) on tri-gate AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs). As w(fin) is reduced, the threshold voltage (V-TH) increases, which is due ...

2019

Fluorescence lifetime imaging with a single-photon SPAD array using long overlapping gates: an experimental and theoretical study

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Arin Can Ülkü

Developing large arrays of single-photon avalanche diodes (SPADs) with on-chip time-correlated single-photon counting (TCSPC) capabilities continues to be a difficult task due to stringent silicon real estate constraints, high data rates and system complex ...

2019

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) ...

IEEE2017

Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Exact synthesis is the problem of finding logic networks that represent given Boolean functions and respect given constraints. With exact synthesis it is possible to find optimum networks, e.g., in size or depth; consequently, it primarily finds applicatio ...

2017

Chip-Level CMOS Co-Integration of ReRAM-Based Non-Volatile Memories

Elmira Shahrabi, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Mahmoud Hadad, Behnoush Attarimashalkoubeh

This work reports a technique to fabricate ReRAM crossbar arrays co-integrated with fully finished 180 nm CMOS technology chips. The proposed integration method enables low- cost ReRAM-CMOS integration and allows the rapid prototyping of complete memory sy ...

Ieee2016