Publications associées à Fan-out

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits

Giovanni De Micheli, Eleonora Testa, Heinz Riener, Siang-Yun Lee

Adiabatic quantum-flux-parametron (AQFP) circuits are a family of superconducting electronic (SCE) circuits that have recently gained growing interest due to their low-energy consumption, and may serve as alternative technology to overcome the down-scaling ...

IEEE2021

Impact of Fin Width on Tri-Gate GaN MOSHEMTs

Elison de Nazareth Matioli, Jun Ma, Luca Nela, Giovanni Santoruvo, Taifang Wang

In this paper, we present a detailed investigation of the impact of fin width (w(fin)) on tri-gate AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs). As w(fin) is reduced, the threshold voltage (V-TH) increases, which is due ...

2019

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos

Traditional logic synthesis faces challenges of meeting the requirements demanded by the many emerging nanotech-nologies that are based on logic models different from standard CMOS. Several emerging nanodevices including Quantum-dot Cellular Automata (QCA) ...

IEEE2017

An Enhanced Design Methodology for Resonant Clock Trees

Giovanni De Micheli, Xifan Tang, Vasileios Pavlidis, Somayyeh Rahimian Omam

Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, sig ...

American Scientific Publishers2013

A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA

Yusuf Leblebici, Christian Piguet, Bahman Kheradmand Boroujeni

A new circuit style is proposed to tune the delay, subthreshold leakage (ISUB), and gate leakage (IG) of high fan-in multiplexer circuits, such as the FPGA Look-Up Table (LUT) and Switch-Box (SB), without increasing the Gate Induced Drain Leakage (GIDL) cu ...

American Scientific Publishers2013

On the Static and Dynamic Behavior of the Germanium Electron-Hole Bilayer Tunnel FET

Mihai Adrian Ionescu, Luca De Michielis, Livio Lattanzio, Nilay Dagtekin

Tunnel FETs (TFETs) are being intensively investigated for their potential in achieving subthermal switching slopes and extremely low leakage currents. Recently, a promising concept has been proposed: the electron-hole bilayer TFET (EHBTFET), which exploit ...

Ieee-Inst Electrical Electronics Engineers Inc2012

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

Andreas Peter Burg, Pascal Andreas Meinerzhagen, Oskar Andersson

Ultra-low power (ULP) biomedical implants and sensor nodes typically require small memories of a few kb, while previous work on reliable subthreshold (sub-Vt) memories targets several hundreds of kb. Standard-cell based memories (SCMs) are a straightforwar ...

2012