Conception de circuits intégrés

Résumé

La conception (ou le design) de circuits intégrés (ou puces électroniques) consiste à réaliser les nombreuses étapes de développement (flot de conception ou design flow) nécessaires pour concevoir correctement et sans erreurs une puce électronique.

Le point d'entrée est une spécification fonctionnelle qui décrit le fonctionnement voulu de la puce, ainsi que des contraintes non fonctionnelles (surface, coût, consommation...).
Le point de sortie est la représentation sous forme d'un fichier informatique (généralement au format GDSII ou plus récemment OASIS) des dessins des masques (layout) de la puce. Ce fichier permet la fabrication des masques (généralement en quartz). Ces masques serviront alors lors de la fabrication de la puce dans les unités de fabrication de semi-conducteurs (fab ou fonderie) pendant les étapes de photolithographie.

De quoi est composé un circuit intégré ? Les circuits intégrés complexes de type SoC (System On Chip ou Système Sur Puce en français

Source officielle

https://fr.wikipedia.org/wiki/Conception_de_circuits_int%C3%A9gr%C3%A9s

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Designing digital circuits well is notoriously difficult. This difficulty stems in part from the very many degrees of freedom inherent in circuit design, typically coupled with the need to satisfy various constraints. In this thesis, we demonstrate how formulations of satisfiability problems can be used automatically to complete a design, or to find a specific design architecture that satisfies certain constraints; how these can be used to create, debug, and optimize designs; and introduce a domain-specific language particularly well-suited for satisfiability-assisted design, debug, and optimization. In the first application, we show how explicit uncertainties called âholesâ can both be natural to use and conducive to the creation of formal satisfiability problems useful for designing circuits. We further develop a Scala-hosted Domain Specific Language (DSL) with appropriate syntactic sugar to make design with holes easy and effective. We then show how, utilizing the same kind of satisfiability formulation, we can automatically instrument a given buggy design to replace suspicious syntax fragments with potentially-correct alternatives. The satisfiability solver then determines if there is any possible set of alternative fragments which fix the bug. We also demonstrate that this approach is reasonably scalable, in part because there is less need for a fully-precise specification in the formulation of the satisfiability problem. We then advance beyond mere hole-filling and show how a tight integration of design elaboration with satisfiability solvers allows totally new approaches. To point, we use this tight integration to create the first known methods to optimize Gate-Level Information Flow Track- ing (GLIFT) model circuits and to make principled trade-offs in their precision. Finally, integrating all the previous work, we propose a more powerful DSL specifically designed to address the shortcomings of the first âhole-fillingâ language. This language, which we call Nasadiya, affords more general integrations of satisfiability into circuit design and optimization, and provides built-in modeling functionality useful for optimizing extra-functional properties like critical path delay and circuit area. We demonstrate the utility of these features by implementing an automatic power optimizer for a popular type of parallel prefix adders.

EPFL2018

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Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Andrew James Becker, Wei Hu, Paolo Ienne, Ryan Charles Kastner

Secure hardware design is a challenging task that goes far beyond ensuring functional correctness. Important design properties such as non-interference cannot be verified on functional circuit models due to the lack of essential information (e.g., sensitivity level) for reasoning about security. Hardware information flow tracking (IFT) techniques associate data objects in the hardware design with sensitivity labels for modeling security-related behaviors. They allow the designer to test and verify security properties related to confidentiality, integrity, and logical side channels. However, precisely accounting for each bit of information flow at the hardware level can be expensive. In this work, we focus on the precision of the IFT logic. The key idea is to selectively introduce only one sided errors ( false positives); these provide a conservative and safe information flow response while reducing the complexity of the security logic. We investigate the effect of logic synthesis on the quality and complexity of hardware IFT and reveal how different logic synthesis optimizations affect the amount of false positives and design overheads of IFT logic. We propose novel techniques to further simplify the IFT logic while adding no, or only a minimum number of, false positives. Additionally, we provide a solution to quantitatively introduce false positives in order to accelerate information flow security verification. Experimental results using IWLS benchmarks show that our method can reduce complexity of GLIFT by 14.47% while adding 0.20% of false positives on average. By quantitatively introducing false positives, we can achieve up to a 55.72% speedup in verification time.

Assoc Computing Machinery2016

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Challenges and Opportunities of Edge AI for Next-Generation Implantable BMIs

Mohammad Ali Shaeri, Mahsa Shoaran

Neuroscience and neurotechnology are currently being revolutionized by artificial intelligence (AI) and machine learning. AI is widely used to study and interpret neural signals (analytical applications), assist people with disabilities (prosthetic applications), and treat underlying neurological symptoms (therapeutic applications). In this brief, we will review the emerging opportunities of on-chip AI for the next-generation implantable brain machine interfaces (BMIs), with a focus on state-of-the-art prosthetic BMIs. Major technological challenges for the effectiveness of AI models will be discussed. Finally, we will present algorithmic and IC design solutions to enable a new generation of AI-enhanced and high-channel-count BMIs.

IEEE2022

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EPFL2018