Publications associées à NOR gate

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

Jean-Michel Sallese, Christophe Lallement

In this letter, we propose to introduce the notion of equivalent capacitance and to generalize the so-called equivalent-thickness concept to model arbitrary shapes of lightly doped nonplanar multigate MOSFETs, without the need to introduce any unphysical p ...

2012

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Mihai Adrian Ionescu, Jean-Michel Sallese, Wladyslaw Grabinski, Mohammad Najmzadeh, Matthieu Berthomé

In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deple ...

Institute of Electrical and Electronics Engineers2012

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Giovanni De Micheli, Jürgen Brugger, Andreea Veronica Savu, Davide Sacchetto, Michail Zervas, Shenqi Xie, Yusuf Leblebici

We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub ...

Elsevier2012

Modeling of Sediment Management for the Lavey Run-of-River HPP in Switzerland

Anton Schleiss, Martin Peter Bieri, Michael Müller

Reservoir sedimentation hinders the operation of the Lavey run-of-river hydropower plant (HPP) on the Rhone River in Switzerland. Deposits upstream of the gated weir and the lateral water intake reduce the flood release capacity and entrain sediments into ...

2012

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Mihai Adrian Ionescu, Didier Bouvet, Wladyslaw Grabinski, Mohammad Najmzadeh

In this work we report an experimental study on accumulation-mode (AM) gate-all-around (GAA) nMOSFETs based on silicon nanowires with uniaxial tensile strain. Their electrical characteristics are studied from room temperature up to ~400 K and carrier mobil ...

2011

Corner Effect and Local Volume Inversion in SiNW FETs

Mihai Adrian Ionescu, Kirsten Emilie Moselund, Luca De Michielis, Luca Selmi

In this paper, a quantitative study of the corner effect and of the local volume inversion on gate-all-around MOSFETs based on numerical simulations has been carried out; different angles and doping levels are compared, in order to understand the impact of ...

Institute of Electrical and Electronics Engineers2011

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

Mihai Adrian Ionescu, Luca De Michielis, Livio Lattanzio, Pierpaolo Palestri, Luca Selmi

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus ...

IEEE2011

Low-Noise Microwave Performance of 0.1 mu m Gate AlInN/GaN HEMTs on SiC

Nicolas Grandjean, Jean-François Carlin, Eric Feltin, Marcus Gonschorek

We report the first microwave noise characterization of AlInN/GaN HEMTs. Transistors with a 0.1 mu m gate implemented on a semi-insulating SiC substrate achieve a maximum current density of 1.92 A/mm at V-GS = 0 V, a measured transconductance g(M) = 480 mS ...

2010

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NOR gate

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Modeling of Sediment Management for the Lavey Run-of-River HPP in Switzerland

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Corner Effect and Local Volume Inversion in SiNW FETs

Hybrid states of Tamm plasmons and exciton-polaritons

Single-Photon Techniques for Standard CMOS Digital ICs

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

Low-Noise Microwave Performance of 0.1 mu m Gate AlInN/GaN HEMTs on SiC

Graph Chatbot

Chattez avec Graph Search

Generalization of the Concept of Equivalent Thickness and Capacitance to Multigate MOSFETs Modeling

Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Local volume depletion/accumulation in GAA Si nanowire junctionless nMOSFETs

Hybrid states of Tamm plasmons and exciton-polaritons

Uniaxially tensile strained accumulation-mode gate-all-around Si nanowire nMOSFETs

Modeling of Sediment Management for the Lavey Run-of-River HPP in Switzerland

Single-Photon Techniques for Standard CMOS Digital ICs

Corner Effect and Local Volume Inversion in SiNW FETs

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

Low-Noise Microwave Performance of 0.1 mu m Gate AlInN/GaN HEMTs on SiC