Concept

NOR gate

Publications associées (79)

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub- ...

2010

Memristive Devices Fabricated with Silicon Nanowire Schottky Barrier Transistors

Giovanni De Micheli, Sandro Carrara, Davide Sacchetto, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

This paper reports on the memory and memristive effects of Schottky barrier field effect transistors (SBFET) with gate-all-around (GAA) configuration and Si nanowire (SiNW) channel. Similar behavior has also been investigated for SBFETs with poly-Si nanowi ...

IEEE Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2010

Characterization of Plasma-Induced Damage of Selectively Recessed GaN/InAlN/AlN/GaN Heterostructures Using SiCl4 and SF6

Nicolas Grandjean, Jean-François Carlin, Marcus Gonschorek

We have investigated an inductively coupled plasma etching recipe using SiCl4 and SF6 with a resulting selectivity >10 for GaN in respect to InAlN. The formation of an etch-resistant layer of AlF3 on InAlN required about 1 min and was noticed by a 4-times- ...

2010

Methodology for the Digital Calibration of Analog Circuits and Systems Using Sub-binary Radix DACs

Maher Kayal, Marc Pastre

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009

Retention in nonvolatile silicon transistors with an organic ferroelectric gate

Mihai Adrian Ionescu, Nava Setter, Alexander Tagantsev, Igor Stolichnov, Didier Bouvet, Giovanni Antonio Salvatore, Sebastian Riester, Roman Gysel

A silicone-based one-transistor nonvolatile memory cell has been implemented by integration of a ferroelectric polymer gate on a standard n- type metal oxide semiconductor field effect transistor. The polarization reversal in the gate results in a stable a ...

2009

Semiconductor device and method of manufacturing a semiconductor device

Mihai Adrian Ionescu, Didier Bouvet, Kirsten Emilie Moselund

The local bending of a silicon nanowire induces tensile strain in the wire due to the stretching of the silicon lattice. This in turn enhances the mobility of the free carriers (electrons) in the direction of transport along the wire. Thus, for example, wh ...

2009

Initialization Mechanism in Kohonen Neural Network Implemented in CMOS Technology

Rafal Tomasz Dlugosz

An initialization mechanism is presented for Kohonen neural network implemented in CMOS technology. Proper selection of initial values of neurons’ weights has a large influence on speed of the learning algorithm and finally on the quantization error of the ...

2008

Prospects for logic-on-a-wire

Giovanni De Micheli, Mihai Adrian Ionescu, David Atienza Alonso, Didier Bouvet, Kirsten Emilie Moselund, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

In this paper we present the top-down fabrication of gate-all-around (GAA) and body-tied @W-gate devices by a combination of etching and oxidation steps resulting in a local silicon-on-insulator structure. The GAA has advantages in terms of enhanced curren ...

2008

Fabrication of MEMS Resonators in Thin SOI

Mihai Adrian Ionescu, Daniel Grogg, Nicoleta-Diana Ciressan

A simple and fast process for micro-electromechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented in this paper. Thin SOI wafers are important for advanced CMOS technology and thus are evaluated as resonator substrates ...

2008

Étude du tomographe de haute résolution pour petits animaux ClearPET par la méthode de Monte Carlo

Martin Rey

The Lausanne ClearPET demonstrator is one of the new generation of high resolution small animal PET scanners. A high resolution PET scanner aims to maximize the signal-to-noise ratio measured in pixels for a given time without compromising spatial resoluti ...

EPFL2007

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