Publications associées à Processeur softcore

Approximate FPGA Implementation of CORDIC for Tactile Data Processing using Speculative Adders

In most robotic and biomedical applications, the interest for real-time embedded systems with tactile ability has been growing. For example in prosthetics, a dedicated portable system is needed for developing wearable devices. The main challenges for such ...

2017

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Paolo Ienne, Mikhail Asiatici, Nithin George

FPGAs offer high performance coupled with energy efficiency making them extremely attractive computational resources within a cloud ecosystem. However, to achieve this integration and make them easy to program, we first need to enable users with varying ex ...

2017

Single-FPGA complete 3D and 2D medical ultrasound imager

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Damien Doy

3D ultrasound (US) acquisition acquires volumetric images, thus alleviating a classical US imaging bottleneck that requires a highly-trained sonographer to operate the US probe. However, this opportunity has not been explored in practice, since 3D US machi ...

IEEE2017

Live Demonstration: Inexpensive 1024-Channel 3D Telesonography System on FPGA

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Damien Doy

Volumetric ultrasound (US) is a very promising development of medical US imaging. An under-exploited advantage of volumetric US is the mitigation of the strict probe positioning constrains necessary to acquire 2D scans, potentially allowing the decoupling ...

2017

1024-Channel 3D Ultrasound Digital Beamformer in a Single 5W FPGA

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Aya Mohamed Naguib Ahmed Ibrahim

3D ultrasound, an emerging medical imaging technique that is presently only used in hospitals, has the potential to enable breakthrough telemedicine applications, provided that its cost and power dissipation can be minimized. In this paper, we present an F ...

IEEE2017

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Paolo Ienne, Grace Zgheib, Yu Lin, Wei Li

The And-Inverter Cone has been introduced as an alternative logic element to the look-up table in FPGAs, since it improves their performance and resource utilization. However, further analysis of the AIC design showed that it suffers from the delay discrep ...

ACM2017

Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer

Jean-Philippe Thiran, Giovanni De Micheli, Federico Angiolini, Marcel Arditi, Aya Mohamed Naguib Ahmed Ibrahim, Ahmet Caner Yüzügüler

We present an efficient FPGA architecture suitable for a medical 3D ultrasound beamformer. We tackle the delay calculation bottleneck, which is the heart and the most critical part of the beam-former, by proposing a computationally efficient design that is ...

Ieee2016

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

LinoSPAD: a time-resolved 256x1 CMOS SPAD line sensor system featuring 64 FPGA-based TDC channels running at up to 8.5 giga-events per second

Edoardo Charbon, Claudio Bruschini, Harald Arjan Robert Homulle, Samuel Burri

LinoSPAD is a reconfigurable camera sensor with a 256x 1 CMOS SPAD (single-photon avalanche diode) pixel array connected to a low cost Xilinx Spartan 6 FPGA. The LinoSPAD sensor's line of pixels has a pitch of 24 pm and 40% fill factor. The FPGA implements ...

Spie-Int Soc Optical Engineering2016

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Processeur softcore

Approximate FPGA Implementation of CORDIC for Tactile Data Processing using Speculative Adders

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Single-FPGA complete 3D and 2D medical ultrasound imager

Live Demonstration: Inexpensive 1024-Channel 3D Telesonography System on FPGA

1024-Channel 3D Ultrasound Digital Beamformer in a Single 5W FPGA

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

LinoSPAD: a time-resolved 256x1 CMOS SPAD line sensor system featuring 64 FPGA-based TDC channels running at up to 8.5 giga-events per second

Graph Chatbot

Chattez avec Graph Search

Live Demonstration: Inexpensive 1024-Channel 3D Telesonography System on FPGA

Approximate FPGA Implementation of CORDIC for Tactile Data Processing using Speculative Adders

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

1024-Channel 3D Ultrasound Digital Beamformer in a Single 5W FPGA

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

LinoSPAD: a time-resolved 256x1 CMOS SPAD line sensor system featuring 64 FPGA-based TDC channels running at up to 8.5 giga-events per second

Single-FPGA complete 3D and 2D medical ultrasound imager

Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer