Publications associées à Loi de Moore

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

Jean-Michel Sallese, Farzan Jazaeri, Ashkhen Yesayan

In this article, we present a theoretical analysis of a junctionless (JL), ion-sensitive, field-effect-transistor (ISFET), self-consistently combining the electrochemical interaction between the semiconductor-insulator interface and the surrounding electro ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Gain-Cell Embedded DRAMs: Modeling and Design Space

Andreas Peter Burg, Adam Shmuel Teman, Robert Giterman, Andrea Bonetti

Among the different types of dynamic random-access memories (DRAMs), gain-cell embedded DRAM (GC-eDRAM) is a compact, low-power, and CMOS-compatible alternative to conventional static random-access memory (SRAM). GC-eDRAM achieves high memory density, as i ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

Small-Signal Approach for Precise Evaluation of Gate Losses in Soft-Switched Wide-Band-Gap Transistors

Elison de Nazareth Matioli, Armin Jafari, Palliyage Srilak Nirmana Perera, Furkan Karakaya

High-frequency switching is favorable for fast transient response, small size of passive components and superior power density, especially in soft-switching topologies. At high frequencies, power dissipation due to consecutive charging/discharging of gate ...

IEEE2020

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Mihai Adrian Ionescu, Igor Stolichnov, Ali Saeidi, Teodor Rosca, Matteo Cavalieri

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by u ...

AMER CHEMICAL SOC2020

Inverse design and demonstration of high-performance wide-angle diffractive optical elements

Toralf Scharf, Dong Cheon Kim

Diffractive optical elements are ultra-thin optical components required for constructing very compact optical 3D sensors. However, the required wide-angle diffractive 2D fan-out gratings have been elusive due to design challenges. Here, we introduce a new ...

OPTICAL SOC AMER2020

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

Andreas Peter Burg, David Ruffieux

Microcontroller systems operating at low supply voltage in near- or sub-threshold regime suffer both from increased effects of PVT (Process, Voltage, Temperature) variation and from a larger share of leakage on overall power due to the reduced frequency. W ...

IEEE2019

Crystal Phase Tuning in Planar Films of III-V Semiconductors

Anna Fontcuberta i Morral, Kirsten Emilie Moselund, Nicolas Tappy

We report on the control of the crystal phase of micron-sized planar III-V semiconductor films grown on top of standard (001) oriented substrates. We achieve this by confining the MOCVD process using SiO2 templates and selecting specific growth planes. We ...

IEEE2019

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

Edoardo Charbon, Fabio Sebastiano

Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is ...

IEEE2019

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Edoardo Charbon, Andrea Ruffino, Yatao Peng, Fabio Sebastiano

Cryogenic solid-state quantum processors require classical control and readout electronics; to achieve compactness and scalability, cryogenic integrated circuits have been recently proposed for this goal. Circulators are widely used in readout circuits, ho ...

2019

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Loi de Moore

Dimensional scaling of high-speed printed organic transistors enabling high-frequency operation

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

Gain-Cell Embedded DRAMs: Modeling and Design Space

Small-Signal Approach for Precise Evaluation of Gate Losses in Soft-Switched Wide-Band-Gap Transistors

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Inverse design and demonstration of high-performance wide-angle diffractive optical elements

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

Crystal Phase Tuning in Planar Films of III-V Semiconductors

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

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Chattez avec Graph Search

Dimensional scaling of high-speed printed organic transistors enabling high-frequency operation

Gain-Cell Embedded DRAMs: Modeling and Design Space

Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs

Inverse design and demonstration of high-performance wide-angle diffractive optical elements

A 6.5-GHz Cryogenic All-Pass Filter Circulator in 40-nm CMOS for Quantum Computing Applications

Small-Signal Approach for Precise Evaluation of Gate Losses in Soft-Switched Wide-Band-Gap Transistors

Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Crystal Phase Tuning in Planar Films of III-V Semiconductors