Concept
Diode logic
Publications associées (67)
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic
Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos
Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...
2020Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic
Giovanni De Micheli, Mathias Soeken, Eleonora Testa, Odysseas Zografos
Emerging technologies such as plasmonics and photonics are promising alternatives to CMOS for high throughput applications, thanks to their waveguide's low power consumption and high speed of computation. Besides these qualities, these novel technologies a ...
IEEE2020A molecular logic gate enables super-resolved imaging of intracellular lipid droplets
Pablo Rivera Fuentes, Adam Miklos Eördögh
Photoactivatable dyes enable single-mol. imaging in biol. Despite progress in the development of new fluorophores and labeling strategies, many cellular compartments remain difficult to image beyond the limit of diffraction in living cells. For example, li ...
2019Threshold Logical Clocks for Asynchronous Distributed Coordination and Consensus
Consensus protocols for asynchronous networks are usually complex and inefficient, leading practical systems to rely on synchronous protocols. This paper attempts to simplify asynchronous consensus by building atop a novel threshold logical clock abstracti ...
2019On the Dynamic Performance of Laterally Gated Transistors
Elison de Nazareth Matioli, Armin Jafari, Catherine Erine, Giovanni Santoruvo
Laterally gated transistors have been proposed as an innovative device architecture in which a semiconducting channel is controlled by side gates. In this sense, the gate can either be in contact with the sidewalls or be separated by a gap. In the latter c ...
2019Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers
Cunxi Yu, Maciej Jerzy Ciesielski
The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2(m)) using GF(2) models of its logi ...
IEEE2018Area and Power Efficient Ultra-Wideband Transmitter Based on Active Inductor
Catherine Dehollain, Kerim Türe, Arnout Jan J Devos, Franco Maloberti
This paper presents the design of an impulse radio ultra-wideband (IR-UWB) transmitter for low-power, short-range, and high-data rate applications such as high density neural recording interfaces. The IR-UWB transmitter pulses are generated by modulating t ...
2018Monolithic Integration of GaN-Based NMOS Digital Logic Gate Circuits with E-Mode Power GaN MOSHEMTs
Elison de Nazareth Matioli, Minghua Zhu
In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-fin ...
IEEE2018Integrated ESOP Refactoring for Industrial Designs
Giovanni De Micheli, Mathias Soeken, Luca Gaetano Amarù, Winston Jason Haaswijk
We present a multi-level logic refactoring algorithm based on exclusive sum-of-product (ESOP) expressions. ESOP expressions are two-level logic representation forms, similar to sum of -product (SOP) expressions. However, ESOPs use EXOR instead of OR operat ...
IEEE2018Multi-level Logic Benchmarks: An Exactness Study
Giovanni De Micheli, Mathias Soeken, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Eleonora Testa, Winston Jason Haaswijk
In this paper, we study exact multi-level logic benchmarks. We refer to an exact logic benchmark, or exact benchmark in short, as the optimal implementation of a given Boolean function, in terms of minimum number of logic levels and/or nodes. Exact benchma ...
Ieee2017