Publications associées à Gigue (électronique)

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Edoardo Charbon, Claudio Bruschini, Myung Jae Lee, Feng Liu

We introduce a new family of single-photon avalanche diodes (SPADs) with enhanced depletion regions in a 55-nm Bipolar-CMOS-DMOS (BCD) technology. We demonstrate how to systematically engineer doping profiles in the main junction and in deep p-well layers ...

Piscataway2024

Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks

Jean-Yves Le Boudec, Ehsan Mohammadpour

Dampers are devices that reduce delay jitter in the context of time-sensitive networks, by delaying packets for the amount written in packet headers. Jitter reduction is required by some real-time applications; beyond this, dampers have the potential to so ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

A Low-Jitter and Low-Spur Charge-Sampling PLL

Edoardo Charbon, Fabio Sebastiano

This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing an ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Edoardo Charbon, Fabio Sebastiano

This paper presents a charge-sampling PLL (CSPLL), that demonstrates the best reported jitter-power FOM of -258.9 dB thanks to its high phase-detection gain and to the removal of the power-hungry buffer driving the phase detector. It also achieves -65 dBc ...

IEEE2020

Spatial covariance improves BCI performance for late ERPs components with high temporal variability

Ricardo Andres Chavarriaga Lozano, Lucian Andrei Gheorghe, Marija Uscumlic, Ruslan Aydarkhanov

Objective. Event Related Potentials (ERPs) reflecting cognitive response to external stimuli, are widely used in brain computer interfaces. ERP waveforms are characterized by a series of components of particular latency and amplitude. The classical ERP dec ...

2020

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work reports a low power implementation of a 60Gb/s NRZ optical receiver (RX) in 14nm bulk CMOS finFET featuring a first-order digital CDR with high jitter tolerance (JTOL). The design includes a single phase-rotator (PR) with low complexity control l ...

2017

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Seyed Armin Tajalli, Yusuf Leblebici, Kiarash Gharibdoust

This paper presents the design and implementation of a multiplying delay-locked loop (MDLL) in 40 nm bulk CMOS process, which can be used as clock and data recovery (CDR) unit in source-synchronous wire-line communications. The MDLL multiplies the referenc ...

Ieee2016

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Giovanni De Micheli, Yusuf Leblebici, Alessandro Cevrero, Kiarash Gharibdoust, Giulia Beanato

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can sa ...

Elsevier2016

Universal dynamics and deterministic switching of dissipative Kerr solitons in optical microresonators

Tobias Kippenberg, Victor Brasch, Maxim Karpov, Hairun Guo, Martin Hubert Peter Pfeiffer, Erwan Guillaume Albert Lucas, Arne Kordts

Temporal dissipative Kerr solitons in optical microresonators enable the generation of ultrashort pulses and low-noise frequency combs at microwave repetition rates. They have been demonstrated in a growing number of microresonator platforms, enabling chip ...

Nature Publishing Group2016

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Gigue (électronique)

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks

A Low-Jitter and Low-Spur Charge-Sampling PLL

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

Spatial covariance improves BCI performance for late ERPs components with high temporal variability

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

Universal dynamics and deterministic switching of dissipative Kerr solitons in optical microresonators

Graph Chatbot

Chattez avec Graph Search

A 10-to-12 GHz 5mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter,-258.9 dB FOM and-65 dBc Reference Spur

A Low-Jitter and Low-Spur Charge-Sampling PLL

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

Doping Engineering for PDP Optimization in SPADs Implemented in 55-nm BCD Process

Design and Analysis of Jitter-Aware Low-Power and High-Speed TSV Links for 3D ICs

A Wideband MDLL with Jitter Reduction Scheme for Forwarded Clock Serial Links in 40 nm CMOS

Spatial covariance improves BCI performance for late ERPs components with high temporal variability

Universal dynamics and deterministic switching of dissipative Kerr solitons in optical microresonators

Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET