Semiconductor device modeling | EPFL Graph Search

Semiconductor device modeling creates models for the behavior of the electrical devices based on fundamental physics, such as the doping profiles of the devices. It may also include the creation of compact models (such as the well known SPICE transistor models), which try to capture the electrical behavior of such devices but do not generally derive them from the underlying physics. Normally it starts from the output of a semiconductor process simulation. Introduction The figure to the right provides a simplified conceptual view of “the big picture.” This figure shows two inverter stages and the resulting input-output voltage-time plot of the circuit. From the digital systems point of view the key parameters of interest are: timing delays, switching power, leakage current and cross-coupling (crosstalk) with other blocks. The voltage levels and transition speed are also of concern. The figure also shows schematically the importance of Ion versus Ioff, which in turn i

Design-oriented Modeling of 28 nm FDSOI CMOS Technology down to 4.2 K for Quantum Computing

Arnout Lodewijk M Beckers, Christian Enz, Louis Hutin, Farzan Jazaeri

In this paper a commercial 28 nm FDSOI CMOS technology is characterized and modeled from room temperature down to 4.2 K. Here we explain the influence of incomplete ionization and interface traps on this technology starting from the fundamental device-physics. We then illustrate how these phenomena can be accounted for in circuit device-models. We find that the design-oriented simplified EKV model can accurately predict the impact of the temperature reduction on the transfer characteristics, back-gate sensitivity, and transconductance efficiency. The presented results aim at extending industry-standard compact models to cryogenic temperatures for the design of cryo-CMOS circuits implemented in a 28 nm FDSOI technology.

2018

Compact modeling of high voltage MOSFETs

Yogesh Singh Chauhan

In the automotive industry, there is a strong trend that has increased the electronics in cars for various functions like fuel injection, electric control of doors and windows, electric chair adjustment, air conditioning etc. The 12V battery used in the present cars will not be sufficient for the increasing number of functions, as a consequence, a change towards 42V batteries will be necessary. For these automotive systems, so called smart power ICs must be used. These are the chips in which the power functionality e.g. control of motor is integrated with logic control. There is also a trend towards operation at high voltages and integrating more intelligence using a microcontroller's RAM/ROM memory and several other sensors and interfaces. The final goal is the integration of a complete system on a single chip, so called power system on chip (SoC). The interest in accurate modeling of high voltage transistors has increased in recent years due to the compatibility of these devices with standard CMOS technology. However, existing LDMOS models are not accurate enough for this task and SPICE models are specially weak for AC performance. The limitation of these models lies in their lack of capability to physically model some of the characteristic phenomena observed in high voltage devices. The increased difficulty is related to complex 2D effects specific to asymmetric high voltage device architectures. This thesis presents the compact modeling of high voltage devices. First, a highly scalable general high voltage MOSFET model, for the first time, is presented, which can be used for any high voltage MOSFET with extended drift region. This model includes physical effects like the quasi-saturation, impact-ionization and self-heating, and a new general model for drift resistance. The model is validated on the measured characteristics of two widely used high voltage devices in the industry i.e. LDMOS and VDMOS devices, and implemented in Verilog-A code and tested on commercial circuit simulators like SABER (Synopsys), ELDO (Mentor Graphics), Spectre (Cadence) and UltraSim (Cadence). The model exhibits excellent scalability with transistor width, drift length, number of fingers and temperature. Second, the compact modeling of lateral non-uniform doping is presented, which has great impact on the AC behavior. Third, the invalidity of Ward-Dutton charge partitioning scheme for lateral non-uniformly doped MOSFET is explained. A novel partitioning scheme is then developed and validated on the device simulation. For the first time, noise modeling of lateral non-uniformly doped MOSFET is carried out and validated on the device simulation.

EPFL2007

Compact modeling of high voltage MOSFETs

Yogesh Singh Chauhan

EPFL2007