Concept

Autonomous peripheral operation

Publications associées (11)

From C/C plus plus Code to High-Performance Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic

High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

ReBeatICG: Real-time Low-Complexity Beat-to-beat Impedance Cardiogram Delineation Algorithm

David Atienza Alonso, Adriana Arza Valdes, Una Pale

This work presents ReBeatICG, a real-time, low-complexity beat-to-beat impedance cardiography (ICG) delineation algorithm that allows hemodynamic parameters monitoring. The proposed procedure relies only on the ICG signal compared to most algorithms found ...

2021

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This paper describes the first practical single-trace side-channel power analysis of SIKE. The attack exploits the nature of elliptic curve point addition formulas which require the same function to be executed multiple times. We target the three point lad ...

2021

REWARD: Design, Optimization, and Evaluation of a Real-Time Relative-Energy Wearable R-Peak Detection Algorithm *

David Atienza Alonso, Jean-Marc Vesin, Lara Orlandic, Sasan Yazdani, Adriana Arza Valdes, Elisabetta De Giovanni

Wearable devices are an unobtrusive, cost-effective means of continuous ambulatory monitoring of chronic cardiovascular diseases. However, on these resource-constrained systems, electrocardiogram (ECG) processing algorithms must consume minimal power and m ...

2019

Flying in dynamic, urban, highly-populated environments represents an open problem in robotics. State-of-the-art (SoA) autonomous Unmanned Aerial Vehicles (UAVs) employ advanced computer vision techniques based on computationally expensive algorithms, such ...

2018

3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

Giovanni De Micheli, Yusuf Leblebici, Luca Benini, Giulia Beanato

Shared L1 memories are of interest for tightly- coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depend ...

2012

A First Step Towards Automatic Application of Power Analysis Countermeasures

Paolo Ienne, Francesco Regazzoni, Philip Brisk, Ali Galip Bayrak

In cryptography, side channel attacks, such as power analysis, attempt to uncover secret information from the physical implementation of cryptosystems rather than exploiting weaknesses in the cryptographic algorithms themselves. The design and implementati ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2011

Optimizing Transactions for Captured Memory

Aleksandar Dragojevic

In this paper, we identify transaction-local memory as a major source of overhead from compiler instrumentation in software transactional memory (STM). Transaction-local memory is memory allocated inside a transaction, which cannot escape (i.e., is capture ...

ACM2009

Microsystem technologies (MST) have become the basis of a large industry. The advantages of MST compared to other technologies provide opportunities for application in implantable biomedical devices. This paper presents a general and broad literature revie ...

2007

The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller

James Pugh, Amélie Victoire Martin

We describe the Lutonium, an asynchronous 8051 microcontroller designed for low Et/sup 2/. In 0.18 /spl mu/m CMOS, at nominal 1.8 V, we expect a performance of 0.5 nJ per instruction at 200 MIPS. At 0.5 V, we expect 4 MIPS and 40 pJ/instruction, correspond ...

2003

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