Concept

Programmable logic array

Publications associées (114)

A Programmable Receiver for Communication Systems and Its Application to Impulse Radio

Pierre-André Farine, Cyril Botteron, Frédéric Chastellain

The design of a programmable receiver for an ultra wideband (UWB) communication is presented. The receiver is using a fast analog to digital converter (ADC) and a field programmable gate array (FPGA) allowing a rapid performance evaluation for various syst ...

Hindawi Publishing Corporation2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems

David Atienza Alonso, Luca Benini, Srinivasan Murali

Field-Programmable Gate Arrays (FPGAs) have become promising mapping fabric for the implementation of System-on-Chip (SoC) platforms, due to their large capacity and their enhanced support for dynamic and partial reconfigurability. Design automation suppor ...

IEEE Press2009

Programmable Logic Circuits based on Ambipolar CNFET

Giovanni De Micheli, David Atienza Alonso, Yusuf Leblebici, Mohamed Haykel Ben Jamaa

Recently, it was demonstrated that the polarity of carbon nanotube field effect transistors can be electrically controlled. In this paper we show how Programmable Logic Arrays (PLA) can be built out of these devices, and we illustrate how they outperform u ...

2008

Self-replication of complex digital circuits in programmable logic devices

Joël Rossier

Nature is an incredibly complex system resulting from the interactions of many different interdependent species, composed of many individual organisms, which are in turn composed of an extremely large number of cells. In multi-cellular organisms, the paral ...

EPFL2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Giovanni De Micheli, David Atienza Alonso

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of runn ...

2008

An Experimental Platform for an Indoor Location and Tracking System

Pierre-André Farine, Cyril Botteron, Frédéric Chastellain

In this paper, an experimental platform for indoor location and tracking using ultra wideband (UWB) impulse radio signals is presented and its performance measured. The platform has been developed entirely using standard electronic components that are comm ...

2008

Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation

Giovanni De Micheli, David Atienza Alonso, Alexandru Emilian Susu

Environmental energy is becoming a feasible alternative to traditional energy sources for ultra low-power devices such as sensor nodes. These devices can run reactive applications that adapt their control flow depending on the sensed data. In order to redu ...

2007

Deep-submicron embedded processor architectures for high-performance, low-cost and low-power

Sylvain Aguirre

Because the market has an insatiable appetite for new functionality, performance is becoming an increasingly important factor. The telecommunication and network domains are especially touched by this phenomenon but they are not the only ones. For instance, ...

EPFL2007

A new interconnect-centric design methodology for high-speed standard cells with crosstalk immunity

Ilhan Hatirnaz

One of the biggest challenges that are facing the Very Large Scale Integrated Circuits (VLSI) technologies today is the significant performance gap (3× to 9×) between full custom circuits and Application Specific Integrated Circuits (ASICs) designed in the ...

EPFL2006

An FPGA-based syntactic parser for large size real-life context-free grammars

Cristian Raul Ciressan

This thesis is at the crossroad between Natural Language Processing (NLP) and digital circuit design. It aims at delivering a custom hardware coprocessor for accelerating natural language parsing. The coprocessor has to parse real-life natural language and ...

EPFL2002

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