Unité de contrôle

Dans un système logique, en particulier dans un processeur, l’unité de contrôle (de commande) commande et contrôle le fonctionnement du système, notamment du chemin de données. Une unité de contrôle est un circuit logique séquentiel qui réalise un automate fini, plus précisément une machine de Moore ou de Mealy, qui génère des signaux de contrôle pour piloter les éléments du chemin de données. Séquenceur câblé Dans un séquenceur câblé, les signaux de contrôle sont produits par un circuit logique ad hoc qui réalise l'automate. Deux méthodes sont possibles :

on peut chercher à réduire le nombre de composants, en particulier le nombre de bascules ; si l'automate compte n états, on peut ainsi concevoir un circuit à log2 n bascules ;
on peut systématiquement attribuer une bascule à chaque état de l'automate ; cela augmente le nombre de bascules, mais simplifie la conception et la mise au point du circuit.

En pratique, les séquenceurs des processeurs réels sont si complexe

À propos de ce résultat

Cette page est générée automatiquement et peut contenir des informations qui ne sont pas correctes, complètes, à jour ou pertinentes par rapport à votre recherche. Il en va de même pour toutes les autres pages de ce site. Veillez à vérifier les informations auprès des sources officielles de l'EPFL.

Publications associées (9)

Improvement of rehabilitation possibilities with the MotionMaker™

Mohamed Bouri, Reymond Clavel, Jacques Fournier, Patrick Métrailler, Carl Schmitt

"MotionMakertrade" is a stationary programmable test and training system for the lower limbs developed at the 'Ecole Polytechnique Federale de Lausanne' with the 'Fondation Suisse pour les Cybertheses'. The system is composed of two robotic orthoses comprising motors and sensors, and a control unit managing the trans- cutaneous electrical muscle stimulation with real-time regulation. The control of the functional electrical stimulation (FES) induced muscle force necessary to mimic natural exercise is ensured by the control unit which receives a continuous input from the position and force sensors mounted on the robot. First results with control subjects showed the feasibility of creating movements by such closed-loop controlled FES induced muscle contractions. To make exercising with the MotionMakertrade safe for clinical trials with spinal cord injured (SCI) volunteers, several original safety features have been introduced. The MotionMakertrade is able to identify and manage the occurrence of spasms. Fatigue can also be detected and overfatigue during exercise prevented

2006

Chargement

Cost-Effective Design of Mesh-of-Tree Interconnect for Multi-Core Clusters with 3-D Stacked L2 Scratchpad Memory

Luca Benini, Giovanni De Micheli

3-D integrated circuits (3-D ICs) offer a promising solution to overcome the scaling limitations of 2-D ICs. However, using too many through-silicon-vias (TSVs) pose a negative impact on 3-D ICs due to the large overhead of TSV (e.g., large footprint and low yield). In this paper, we propose a new TSV sharing method for a circuit-switched 3-D mesh-of-tree (MoT) interconnect, which supports high-throughput and low-latency communication between processing cores and 3-D stacked multibanked L2 scratchpad memory. The proposed method supports traffic balancing and TSV-failure tolerant routing. The proposed method advocates a modular design strategy to allow stacking multiple identical memory dies without the need for different masks for dies at different levels in the memory stack. We also investigate various parameters of 3-D memory stacking (e.g., fabrication technology, TSV bonding technique, number of memory tiers, and TSV sharing scheme) that affect interconnect latency, system performance, and fabrication cost. Compared to conventional MoT interconnect that is straightforwardly adapted to 3-D integration, the proposed method yields up to (times 2.11) and (times 1.11) improvements in terms of cost efficiency (i.e., performance/cost) for microbump TSV bonding and direct Cu–Cu TSV bonding techniques, respectively.

Institute of Electrical and Electronics Engineers2015

Chargement

i-DPs CGRA: An Interleaved-Datapaths Reconfigurable Accelerator for Embedded Bio-signal Processing

Giovanni Ansaloni, David Atienza Alonso, Soumya Subhra Basu, Loris Gérard Duch, Miguel Peon Quiros

Smart edge sensors for bio-signal monitoring must support complex signal processing routines within an extremely small energy envelope. Coarse-Grained Reconfigurable Arrays (CGRAs) are good candidates for tackling these conflicting objectives because, thanks to their flexibility and high computational density, they can efficiently support the computational hot-spots characterizing bio-DSP applications. The Interleaved- Datapaths (i-DPs) CGRA presented in this paper further leverages the benefits of this architectural paradigm, focusing on ultralow energy operation. Its defining feature is the complex design of its computing cells, which, by embedding multiple i-DPs, allow a high ratio between computing and control logic, effectively speeding up computations, and resulting in a marginal impact on the required IC area. Interleaved datapaths increase the energy efficiency of up to 33 %, with respect to a single-DP alternative, when executing common kernels in the multi-lead ECG signal processing field.

2019

Chargement

Afficher plus

Personnes associées

Aucun résultat

Unités associées

Aucun résultat

Concepts associés (32)

Concepts associés

Chargement

Cours associés (9)

Cours associés

Chargement

Séances de cours associées (15)

Séances de cours associées

Chargement

Central processing unit

A central processing unit (CPU)—also called a central processor or main processor—is the most important processor in a given computer. Its electronic circuitry executes instructions of a computer pr

Instruction set architecture

In computer science, an instruction set architecture (ISA), also called computer architecture, is an abstract model of a computer. A device that executes instructions described by that ISA, such as

Matériel informatique

Un matériel informatique (en anglais : hardware) est une pièce ou composant d'un appareil informatique. C'est la partie physique de l’informatique elle est appairée avec le logiciel (software ou fir

EE-334: Digital systems design

Students will acquire basic knowledge about methodologies and tools for the design, optimization, and verification of custom digital systems/hardware. They learn how to design synchronous digital circuits on register transfer level, analyse their timing and implement them in VHDL and on FPGAs.

EE-518: Analog circuits for biochip

Introduction to analog CMOS design for Remote Biosensors on Chip. Understanding and designing of active and remotely powered biosensing systems. Basic understanding of eh wireless transmission of teh obtained signals.

EE-519: Bioelectronics and biomedical microelectronics

The course covers the fundaments of bioelectronics and integrated microelectronics for biomedical and implantable systems. Issues and trade-offs at the circuit and systems levels of invasive microelectronic systems as well as their eluding designs, methods and classical implementations are discussed