Serial port

Résumé

On computers, a serial port is a serial communication interface through which information transfers in or out sequentially one bit at a time. This is in contrast to a parallel port, which communicates multiple bits simultaneously in parallel. Throughout most of the history of personal computers, data has been transferred through serial ports to devices such as modems, terminals, various peripherals, and directly between computers. While interfaces such as Ethernet, FireWire, and USB also send data as a serial stream, the term serial port usually denotes hardware compliant with RS-232 or a related standard, such as RS-485 or RS-422. Modern consumer personal computers (PCs) have largely replaced serial ports with higher-speed standards, primarily USB. However, serial ports are still frequently used in applications demanding simple, low-speed interfaces, such as industrial automation systems, scientific instruments, point of sale systems and some industrial and consumer products. Se

Source officielle

https://en.wikipedia.org/wiki/Serial_port

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Publications associées (6)

Six shades lighter: a bit-serial implementation of the AES family

Muhammed Fatih Balli, Subhadeep Banik, Sergio Roldán Lombardía

Recently, cryptographic literature has seen new block cipher designs such as PRESENT, GIFT or SKINNY that aim to be more lightweight than the current standard, i.e., AES. Even though AES family of block ciphers were designed two decades ago, they still remain as the de facto encryption standard, with AES-128 being the most widely deployed variant. In this work, we revisit the combined one-in-all implementation of the AES family, namely both encryption and decryption of each AES-128/192/256 as a single ASIC circuit. A preliminary version appeared in Africacrypt 2019 by Balli and Banik, where the authors design a byte-serial circuit with such functionality. We improve on their work by reducing the size of the compact circuit to 2268 GE through 1-bit-serial implementation, which achieves 38% reduction in area. We also report stand-alone bit-serial versions of the circuit, targeting only a subset of modes and versions, e.g., AES-192 and AES-256. Our results imply that, in terms of area, AES-192 and AES-256 can easily compete with the larger members of recently designed SKINNY family, e.g., SKINNY-128-256, SKINNY-128-384. Thus, our implementations can be used interchangeably inside authenticated encryption candidates such as SKINNY-AEAD/-HASH, ForkAE or Romulus in place of SKINNY.

2021

Chargement

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The bit-sliding paper of Jean et al. (CHES 2017) showed that the smallest-size circuit for SPN based block ciphers such as AES, SKINNY and PRESENT can be achieved via bit-serial implementations. Their technique decreases the bit size of the datapath and naturally leads to a significant loss in latency (as well as the maximum throughput). Their designs complete a single round of the encryption in 168 (resp. 68) clock cycles for 128 (resp. 64) bit blocks. A follow-up work by Banik et al. (FSE 2020) introduced the swap-and-rotate technique that both eliminates this loss in latency and achieves even smaller footprints. In this paper, we extend these results on bit-serial implementations all the way to four authenticated encryption schemes from NIST LWC. Our first focus is to decrease latency and improve throughput with the use of the swap-and-rotate technique. Our block cipher implementations have the most efficient round operations in the sense that a round function of an n-bit block cipher is computed in exactly n clock cycles. This leads to implementations that are similar in size to the state of the art, but have much lower latency (savings up to 20 percent). We then extend our technique to 4- and 8-bit implementations. Although these results are promising, block ciphers themselves are not end-user primitives, as they need to be used in conjunction with a mode of operation. Hence, in the second part of the paper, we use our serial block ciphers to bootstrap four active NIST authenticated encryption candidates: SUNDAE-GIFT, Romulus, SAEAES and SKINNY-AEAD. In the wake of this effort, we provide the smallest block-cipher-based authenticated encryption circuits known in the literature so far.

2020

Chargement

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The power produced by a photovoltaic module is not simply the sum of the powers of its constituents cells. The difference stems from a number of so-called “cell-to-module” (CTM) gain or loss mechanisms. These are getting more and more attention as improvements in cell efficiency are becoming harder to achieve. This work focuses on two CTM mechanisms: the gain due to the recapture of light hitting the apparent backsheet in the “empty” spaces around the cells and the loss from the serial connection of “mismatched” cells i.e. with different maximum power points. In general, for insulation purposes, the spaces on the edges of modules are larger than the spacing between cells. This study reveals that, when reflective backsheets are used, these “edge spaces” provide an additional current boost to the cells placed at the edges that can lead to a 0.5% gain in the output power of modules (with 60 or 72 cells). This location-dependent current boost adds to the usual variations in cell characteristics dictated by the binning size and results in larger “cell-to-cell mismatch losses”. However, the simulations reveal that for short-circuit current bin size smaller than 5%, this additional mismatch loss is lower than 0.05%. All considered, this study demonstrates that the spaces at the edges of PV modules have a significant impact on the cell to module ratios (≈+0.5%abs or ≈16% of the CTM gains) when reflective backsheets are used.

2018

Chargement

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