Davide Sacchetto

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Publications associées (52)

Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Michele De Marchi, Pierre-Emmanuel Julien Marc Gaillardon, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack, Marios Barlas

This work presents the co-integration of resistive random access memory crossbars within a 180nm Read-Write CMOS chip. TaOx-based ReRAMs have been fabricated and characterized with materials and process steps compatible with the CMOS Back-End-of ...

Institute of Electrical and Electronics Engineers2016

Resistive Switching Element and Use Thereof

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Shashi Kanth Bobba, Tugba Demirci

A bipolar resistive switching device including an electrically conductive bottom electrode, a stack of transition metal oxides layers, a number of transition metal oxide layers being equal or greater than 2, the stack including: at least one MOx layer, at ...

2016

Monolithic fabrication of silicon nanowires bridging thick silicon structures

Georg Fantner, Davide Sacchetto, Yusuf Leblebici, Oliver Peric, Zuhal Tasdemir

2015

Low-Voltage Read/Write Circuit Design for Transistorless ReRAM Crossbar Arrays in 180nm CMOS Technology

Davide Sacchetto, Yusuf Leblebici, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This paper presents a read-write design solution for passive ReRAM crossbar memory arrays to overcome the sneak current paths problem. The proposed circuitry includes an auto-calibration feature to overcome the sneak current effects during the READ operati ...

2015

Graphene Field Effect Devices Operating in Differential Circuit Configuration

Davide Sacchetto, Yusuf Leblebici, Clemens Benedict Nyffeler

We study the concept of a basic building block for circuits using differential signaling and being based on graphene field effect devices. We fabricated a number of top-gated graphene FETs using commercially available graphene and employing electron beam l ...

Elsevier2015

Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Jury Sandrini, Tugba Demirci, Maxime Victor Thammasack

This work reports on a heterogeneous integration of resistive memories into the Back-End-of-the-Line of 180nm standard CMOS foundry chips. A TaOx-based ReRAM technology with materials and processes fully CMOS compatible has been developed and characterized ...

Elsevier2015

Cmos compatible non-volatile latch and d-flip flop using resistive switching materials

Davide Sacchetto, Yusuf Leblebici, Tugba Demirci

A non-volatile latch circuitry, comprising a Re RAM cell configured to store a final value of the non-volatile latch circuitry; a data selection circuitry configured to connect or disconnect a data input to a plus voltage node and a minus voltage node of t ...

2014

Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity

Giovanni De Micheli, Davide Sacchetto, Yusuf Leblebici, Jian Zhang, Pierre-Emmanuel Julien Marc Gaillardon, Michele De Marchi

Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the ...

Institute of Electrical and Electronics Engineers2014

Graphene Field Effect Devices Operating in Differential Configuration

Davide Sacchetto, Yusuf Leblebici, Clemens Benedict Nyffeler

After decades of miniaturization and performance tuning, Silicon electronics is approaching its technological limits. In the search for alternative transistor channel materials, Graphene has been given much attention since its discovery in 2004, mainly bec ...

2014

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

Giovanni De Micheli, Andreas Peter Burg, Davide Sacchetto, Yusuf Leblebici, Pierre-Emmanuel Julien Marc Gaillardon, Pascal Andreas Meinerzhagen

The total power budget of Ultra-Low Power (ULP) VLSI Systems-on-Chip (SoCs) is often dominated by the leakage power of embedded memories as well as status registers. On the one hand, supply voltage scaling down to the near-threshold (near-VT

Institute of Electrical and Electronics Engineers2014

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