Adaptive Weight Change Mechanism for Kohonens's Neural Network Implemented in CMOS 0.18 μm Technology

Rafal Tomasz Dlugosz
2007
Article de conférence

In this paper, we present a block of adaptive weight change (AWC) mechanism for analog current-mode Kohonen's Neural Network (KNN) implemented in CMOS 0.18 μm technology. As some other essential building blocks of KNNs dealing with the calculations of the Euclidean distance, formation of a conscience mechanism and a determination of the winner-takes-all (WTA) circuits have been already developed, the AWC forms another essential step towards the realization of the network. We show that the proposed network works with small values of analog signals thus resulting in low power dissipation and chip area when compared with digital realizations of KNNs. Each neuron occupies chip area equal to about 1000 μm2 and dissipates 20 μW of power for 20 MHz input data rate.

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Rafal Tomasz Dlugosz
2007
Article de conférence

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https://infoscience.epfl.ch/record/167720?ln=fr

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CMOS Implementation of Low Power Kohonen’s Neural Network for Medical Applications

Rafal Tomasz Dlugosz

Recently, artificial intelligence (AI) systems gain an increasing popularity and their development is fast. One of the most important fields of the AI system development are artificial neural networks (ANN’s) which, due to continuous progress in microelectronics and integrated circuits (IC) manufacturing, can be realized as large integrated blocks. Designers of such IC ANN’s take inspiration from biological networks. Networks of this type operate with analog signals, include a big number of neurons and a still bigger number of interconnections between them and, as a result, are able to process the information in parallel on a large scale. Recent advances in digital CMOS technologies enable implementation of different analog circuits in a VLSI integrated circuit form. The design and optimization efforts go towards reducing power dissipation, which is especially important in various diagnostic applications.

2007

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This paper presents a digital, transistor level implemented neo-fuzzy neural network. This type of neural network is particularly well suited for real-time applications like those encountered in signal processing and nonlinear system identification. We consider in detail a flexible reconfigurable circuit of a single nonlinear synapse of this network. When combining such circuits, single-layer or multilayer networks can be designed. The advantages of the proposed circuit come in the form of reduced redundancy, high data rate due to parallel operation, low power consumption, and an overall flexibility of system configuration.

Technical University of Lodz2010

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Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology

Rafal Tomasz Dlugosz

This paper presents a programmable analog current-mode circuit used to calculate the distance between two vectors of currents, following two distance measures. The Euclidean (L2) distance is commonly used. However, in many situations, it can be replaced with the Manhattan (L1) one, which is computationally less intensive, whose realization comes with less power dissipation and lower hardware complexity. The presented circuit can be easily reprogrammed to operate with one of these distances. The circuit is one of the components of an analog winner takes all neural network (NN) implemented in the complementary metal-oxide-semiconductor 0.18-mu m technology. The learning process of the realized NN has been successfully verified by the laboratory tests of the fabricated chip. The proposed distance calculation circuit (DCC) features a simple structure, which makes it suitable for networks with a relatively large number of neurons realized in hardware and operating in parallel. For example, the network with three inputs occupies a relatively small area of 3900 mu m(2). When operating in the L2 mode, the circuit dissipates 85 mu W of power from the 1.5 V voltage supply, at maximum data rate of 10 MHz. In the L1 mode, an average dissipated power is reduced to 55 mu W from 1.2 V voltage supply, while data rate is 12 MHz in this case. The given data rates are provided for the worst case scenario, where input currents differ by 1%-2% only. In this case, the settling time of the comparators used in the DCC is quite long. However, that kind of situation is very rare in the overall learning process.

Institute of Electrical and Electronics Engineers2016

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