This thesis presents the fabrication and characterization of organic thin film transistors (TFTs) on flexible polymer substrates and the development of compliant stencil lithography to significantly improve the patterning resolution on full-wafer scale. Polymers and organic semiconductors have gained increasing attention during the last years. Today, organic semiconductors are envisioned as a viable alternative to traditional TFTs based on inorganic materials. Organic TFTs can be a solution for device flexibility, cost-efficient fabrication, low-temperature processing and large area patterning. However, up to now they cannot keep up with the performance of TFTs based on single-crystalline inorganic semiconductors because of their low switching speeds. Due to the sensitivity of polymers and organic semiconductors to solvents and high temperatures, stencil lithography is a promising patterning technique for such materials. Stencil lithography is based on the principle of the shadow mask technique, which is a parallel process with high spatial resolution down to submicrometer scale. It is a solvent-free patterning method without need of elevated temperatures. The stencil is aligned and clamped to the substrate and the required material is deposited through the stencil. Finally the stencil is removed, resulting in a patterned substrate. A typical stencil is made of low-stress silicon nitride (SiN) membranes supported by bulk silicon (Si). The membranes are released by combined dry and wet etching and contain design-specific micro- and nanoapertures. Stencil lithography was used to pattern titanium-gold (Ti-Au) wires on flexible polymer substrates. The wire resistivity was analyzed by 2-point and 4-point measurements and was found to be comparable with the resistivity of a Ti-Au thin film on a Si wafer. Stencil lithography was also applied to fabricate organic TFTs on a rigid Si substrate as the back gate contact. Polyimide (PI) or silicon dioxide (SiO2) was used as the dielectric layer while pentacene was tested as the organic semiconductor. Source-drain (S/D) Au top contacts were patterned by stencil lithography defining transistor channel lengths down to 5 µm. Pentacene TFTs with different film thicknesses were characterized on both dielectrics. The organic TFT fabrication on rigid Si substrates was used to evaluate pentacene films deposited on a PI dielectric. They have shown continuous pentacene films and similar characteristics compared to SiO2 as the dielectric layer. In a next step pentacene TFTs on a flexible 12 µm thin PI substrate were fabricated on full-wafer scale using a Si wafer as a rigid support. The gate contacts were patterned locally and PI was used as the dielectric material. Pentacene and S/D Au contacts were patterned by applying aligned full-wafer stencil lithography for channel lengths down to 2:5 µm. The yield of 72 pentacene TFTs was as high as 91.5 % and the average apparent mobility μ was (5.0 ± 0.7) · 10-2 cm2/Vs. The pentacene TFTs have been characterized both before and after peeling the flexible PI film off the rigid Si support, showing a to (83 ± 4) % reduced apparent mobility μ. Pentacene TFTs were also characterized during and after exposing the PI substrate to tensile stress. It was found that uniaxial stretching experiments reduced the apparent mobility μ to (71 ± 3) % when the applied strain ε was increased to 2.6 %. After releasing the applied strain ε the apparent mobility μ recovered partially to (81 ± 4) % of its initial value. Cycling strain applied to the PI substrate changed the apparent mobility μ distinctively within the first 1000 cycles compared to the reference TFTs. Further stretching cycles decreased the performance of stretched pentacene TFTs similar as the reference TFTs. After 28'000 cycles of 2.7 % applied strain ε the apparent mobility μ was reduced to (42 ± 3) %. In parallel to the mentioned experiment, a degradation of the pentacene film over time was monitored. The apparent mobility μ was significantly reduced to (61 ± 2) % of its initial value. A known drawback in stencil lithography is the so-called blurring, which is the loss of resolution during the pattern transfer. The main cause of the blurring is the gap between the stencil membrane and the substrate surface. The origin of the gap has several reasons such as the non-planarity of the substrate or different curvatures of stencil and substrate on full-wafer scale. The variation of the wafer curvature due to unsymmetrical patterning of front- and backside of the wafer was monitored during stencil fabrication. One of the major finding is that an increased curvature of the stencil results in an increased gap and therefore reduces the resolution of stencil lithography. Therefore, a more sophisticated stencil based on compliant membranes is proposed in order to minimize the gap and improve the resolution of pattern transfer on full-wafer scale. Compliant membranes are mechanically decoupled from a rigid Si frame by means of four non-planar cantilevers. Compliant membranes are protruding parts, which adapt to the surface independently in order to reduce the gap between a membrane and its substrate. Finite element method (FEM) simulations have shown that compliant membranes can vertically deflect 40 µm, which is a typical maximal gap that can occur between stencil membrane and substrate. Microapertures were defined using ultraviolet (UV) lithography and nanoapertures, down to 200nm in diameter, using focused ion beam (FIB). An aluminum (Al) layer was evaporated through compliant and non-compliant membranes on a Si wafer. Subsequent scanning electron microscopy (SEM) characterizations have shown that the use of a compliant stencil improves significantly the resolution on large area. The geometrical blurring was 95 % and the halo more than 75 % smaller compared to standard (i.e. non-compliant) full-wafer stencil lithography. The results of this thesis demonstrate stencil lithography as a reliable fabrication method for metallic microstructures and organic pentacene TFTs on flexible PI substrates and represent a breakthrough towards improved resolution in full-wafer compliant stencil lithography.
EPFL2010
