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Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Publications associées (50)

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The design of Wren, a Fast and Scalable Transactional Causally Consistent Geo-Replicated Key-Value Store

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

This paper presents the design of Wren, a new geo-replicated key-value store that achieves Transactional Causal Consistency. Wren leverages two design choices to achieve higher performance and better scalability than existing systems. First, Wren uses hybr ...

2017

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Okapi is a new causally consistent geo-replicated key-value store. Okapi leverages two key design choices to achieve high performance. First, it relies on hybrid logical/physical clocks to achieve low latency even in the presence of clock skew. Second, Oka ...

2017

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herei ...

2016

Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits

Hassan Ghasemzadeh Mohammadi

Substantial downscaling of the feature size in current CMOS technology has confronted digital designers with serious challenges including short channel effect and high amount of leakage power. To address these problems, emerging nano-devices, e.g., Silicon ...

EPFL2016

Computing the Impact of White and Flicker Noise in Continuous-Time Integrator-Based ADCs

Maher Kayal, Adil Koukab, Paul Stanislas Gosselin

From first-order incremental Sigma Delta converters to controlled-oscillator-based converters, many ADC architectures are based on the continuous-time integration of the input signal. However, the accuracy of such converters cannot be properly estimated wi ...

Ieee2016

Signaling in 3-D integrated circuits, benefits and challenges

Somayyeh Rahimian Omam

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuit ...

EPFL2015

Method for code evaluation using ISI ratio

Mohammad Amin Shokrollahi, Ali Hormati

2015

This paper presents a high-voltage, high-current implantable cortical stimulation integrated circuit aiming at supporting rehabilitation of patients suffering from stroke. In this context, a large area of the motor cortex needs to be stimulated, requiring ...

2015

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

Andreas Peter Burg, Adam Shmuel Teman, Andrea Bonetti

Dual-edge-triggered (DET) synchronous operation is a very attractive option for low-power, high-performance designs. Compared to conventional single-edge synchronous systems, DET operation is capable of providing the same throughput at half the clock frequ ...

2015

Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache

Giovanni De Micheli, Siang-Yun Lee

The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power d ...

2014